Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć, Michael Niewöhner.

Patch set 6:Code-Review +1

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9 comments:

• Commit Message:

  • Patch Set #6, Line 8:

    Are there any known problems?

• File src/mainboard/clevo/tgl-u/Kconfig:

  • Patch Set #3, Line 13: MAINBOARD_HAS_LPC_TPM

    MEMORY_MAPPED_TPM

    Done

• File src/mainboard/clevo/tgl-u/Kconfig.name:

  • Patch Set #1, Line 5: select BOARD_CLEVO_NV4X_BASE

    I saw patches shifting these selects to the Kconfig.name to Kconfig files, e.g. CB:62816 […]

    Done

• File src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb:

  • Patch Set #6, Line 13:

    # Disable DPTF
    	register "dptf_enable" = "0"
    

    This can be dropped, default is 0

  • Patch Set #6, Line 22: required

    Is S0ix actually required?

  • Patch Set #6, Line 115: device ref peg on

    Add "smbios_slot_desc"?

  • Patch Set #6, Line 261: Pantone ROM

    I wonder what this EEPROM is used for.

  • Patch Set #6, Line 308: register "PcieRpEnable[10]" = "1"

    register "PcieRpSlotImplemented[10]" = "1"

    Also, add "smbios_slot_desc"?

• File src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c:

  • Patch Set #6, Line 12: params->CpuPcieRpAdvancedErrorReporting[0] = 0;

    I'd also add this:

     params->CpuPcieRpSlotImplemented[0] = 1;

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