December 2021 - coreboot-gerrit

Change in coreboot[master]: src/arch/x86/exit_car: Add proper x86_64 code
by Patrick Rudolph (Code Review) Dec. 3, 2021

Dec. 3, 2021

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59873 ) Change subject: src/arch/x86/exit_car: Add proper x86_64 code ...................................................................... src/arch/x86/exit_car: Add proper x86_64 code Don't truncate upper bits in assemlby code and thus allow loading of postcar stage above 4GiB. Tested on qemu. Change-Id: I42d1086f1220e44076ccf613244fc3c6d804805b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/exit_car.S 1 file changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/59873/1 diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 9b89ffb..5d1ffdc 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -111,13 +111,20 @@ #if CONFIG(SOC_SETS_MSRS) +#if ENV_X86_64 + mov %rsp, %rbp + + /* Need to align stack to 16 bytes at the call instruction. Therefore + account for the 1 push. */ + movq $0xfffffffffffffff0, %rax + and %rax, %rsp + mov %rbp, %rdi +#else mov %esp, %ebp /* Need to align stack to 16 bytes at the call instruction. Therefore account for the 1 push. */ andl $0xfffffff0, %esp -#if ENV_X86_64 - mov %rbp, %rdi -#else + sub $12, %esp push %ebp #endif @@ -125,10 +132,18 @@ call soc_set_mtrrs /* Ignore fixing up %esp since we're setting it a new value. */ +#if ENV_X86_64 + /* rax: new top_of_stack with setup_stack_and_mtrrs data removed */ + mov %rax, %rsp + /* Align stack to 16 bytes at call instruction. */ + movq $0xfffffffffffffff0, %rax + and %rax, %rsp +#else /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */ movl %eax, %esp /* Align stack to 16 bytes at call instruction. */ andl $0xfffffff0, %esp +#endif call soc_enable_mtrrs #else /* CONFIG_SOC_SETS_MSRS */ /* Clear variable MTRRs. */ @@ -174,8 +189,14 @@ wrmsr #endif /* CONFIG_SOC_SETS_MSRS */ +#if ENV_X86_64 + /* Align stack to 16 bytes at call instruction. */ + movq $0xfffffffffffffff0, %rax + and %rax, %rsp +#else /* Align stack to 16 bytes at call instruction. */ andl $0xfffffff0, %esp +#endif /* Call into main for postcar. */ call main /* Should never return. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42d1086f1220e44076ccf613244fc3c6d804805b Gerrit-Change-Number: 59873 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mainboard/emulation/qemu-i440fx: Fix struct packing
by Patrick Rudolph (Code Review) Dec. 3, 2021

Dec. 3, 2021

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59872 ) Change subject: src/mainboard/emulation/qemu-i440fx: Fix struct packing ...................................................................... src/mainboard/emulation/qemu-i440fx: Fix struct packing On x86_64 the struct isn't packed, causing the fw_cfg parser to return invlid memory entries (possible others as well) through fw_cfg. Fix that by packing all structs. Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/59872/1 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index e972f54..817d1a5 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -69,18 +69,18 @@ uint16_t select; /* write this to 0x510 to read it */ uint16_t reserved; char name[FW_CFG_MAX_FILE_PATH]; -} FWCfgFile; +} __packed FWCfgFile; typedef struct FWCfgFiles { uint32_t count; FWCfgFile f[]; -} FWCfgFiles; +} __packed FWCfgFiles; typedef struct FwCfgE820Entry { uint64_t address; uint64_t length; uint32_t type; -} FwCfgE820Entry __attribute((__aligned__(4))); +} __packed FwCfgE820Entry __attribute((__aligned__(4))); #define SMBIOS_FIELD_ENTRY 0 @@ -91,7 +91,7 @@ uint8_t headertype; uint8_t tabletype; uint16_t fieldoffset; -} FwCfgSmbios; +} __packed FwCfgSmbios; /* FW_CFG_ID bits */ #define FW_CFG_VERSION 0x01 @@ -113,6 +113,6 @@ uint32_t control; uint32_t length; uint64_t address; -} FwCfgDmaAccess; +} __packed FwCfgDmaAccess; #endif /* FW_CFG_IF_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560 Gerrit-Change-Number: 59872 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/arch/x86/exit_car: Fix regression on x86_64
by Patrick Rudolph (Code Review) Dec. 3, 2021

Dec. 3, 2021

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59871 ) Change subject: src/arch/x86/exit_car: Fix regression on x86_64 ...................................................................... src/arch/x86/exit_car: Fix regression on x86_64 The commit d023909b "treewide: Disable R_AMD64_32S relocation support" introduced clflush cbmem_top() instead of _cbmem_top_ptr, which isn't intended. Fix that by providing the correct address to clflush. Change-Id: If74591e7753cd9c3c097516430a212d416f53e4d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/exit_car.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/59871/1 diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 527a3cb..9b89ffb 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -62,7 +62,7 @@ btl $CPUID_FEATURE_CLFLUSH_BIT, %edx jnc skip_clflush #if ENV_X86_64 - movabs _cbmem_top_ptr, %rax + movabs $_cbmem_top_ptr, %rax clflush (%rax) #else clflush _cbmem_top_ptr -- To view, visit https://review.coreboot.org/c/coreboot/+/59871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74591e7753cd9c3c097516430a212d416f53e4d Gerrit-Change-Number: 59871 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/mmu: Port armv8 MMU to x86_64
by Patrick Rudolph (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Patrick Rudolph. Patrick Rudolph has uploaded a new patch set (#18) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30119 ) Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... arch/x86/mmu: Port armv8 MMU to x86_64 Add functions to set up page tables for long mode. In addition generate new page tables where necessary: - before CBMEM setup, if CBMEM is above 4GiB - after CBMEM setup, if CBMEM is above 4GiB - at end of BS_DEV_RESOURCES in CBMEM At end of BS_DEV_RESOURCES the memory map is fully known and the page tables can be properly generated based on the memory resources. This allows the CPU to access all DRAM and MMIO even beyond 4GiB. Right now there's no use case for this, but the code is necessary to: - Load stages above 4GiB - Load payloads above 4GiB - Install tables (like CBMEM/ACPI/SMBIOS) above 4GiB - allow coreboot PCI drivers to access BARs mapped above 4GiB Tested on prodrive/hermes: Still boots to payload. Doesn't affect existing x86_32 code. Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/Makefile.inc A src/arch/x86/include/arch/mmu.h A src/arch/x86/mmu-ramstage.c A src/arch/x86/mmu-romstage.c A src/arch/x86/mmu.c M src/commonlib/include/commonlib/cbmem_id.h M src/lib/imd_cbmem.c 7 files changed, 630 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30119/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/30119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 30119 Gerrit-PatchSet: 18 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
by Sridhar Siricilla (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Arthur Heymans, Nico Huber, Paul Menzel, Tim Wawrzynczak, Ravindra, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 ) Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/59359/comment/cfa07ca2_09431bd2 PS3, Line 152: acpigen_write_dword(core_id); > Correct, I have updated the patch that doesn't use bitmask. Ack https://review.coreboot.org/c/coreboot/+/59359/comment/3aecb99d_aec54760 PS3, Line 98: void acpi_write_xppc_method(int core_id) : { : struct cpu_hybrid cpu_hybrid_info; : : acpi_get_cpu_hybrid_info(&cpu_hybrid_info); : acpigen_write_method(XPPC_PACKAGE_NAME, 1); : : if (cpu_is_nominal_freq_supported()) { : : /* : * If Nominal Frequency is supported, update Nominal Frequency and set core's : * Nominal Performance to a scaling factor which depends on core type(big or : * small). : */ : acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 22, : cpu_hybrid_info.nominal_freq); : : /* LOCAL2_OP = (CORE >> core_id) & 1 */ : acpigen_emit_byte(SHIFT_RIGHT_OP); : acpigen_write_integer(cpu_hybrid_info.type_mask); : acpigen_emit_byte(ARG0_OP); : acpigen_emit_byte(LOCAL1_OP); : acpigen_write_and(LOCAL1_OP, ONE_OP, LOCAL2_OP); : : /* : * If core id is big Core, then set big core's scaling factor : * to core's nominal frequency otherwise set small core's scaling factor. : */ : acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); : acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 3, : cpu_hybrid_info.big_core_nom_perf); : acpigen_write_else(); : acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 3, : cpu_hybrid_info.small_core_nom_perf); : acpigen_pop_len(); : } : : acpigen_emit_byte(RETURN_OP); : acpigen_emit_namestring(CPPC_PACKAGE_NAME); : acpigen_pop_len(); : } : : void acpigen_write_CPPC_hybrid_method(int core_id) : { : char scope[16]; : : if (core_id == 0) : snprintf(scope, 12, XPPC_PACKAGE_NAME, 0); : else : snprintf(scope, 16, CONFIG_ACPI_CPU_STRING "." XPPC_PACKAGE_NAME, 0); : : acpigen_write_method("_CPC", 0); : acpigen_emit_byte(RETURN_OP); : acpigen_emit_namestring(scope); : acpigen_write_dword(core_id); : acpigen_pop_len(); > >Each CPU has _CPC method and they all use the implementation called XPPC_PACKAGE_NAME of CPU0? Migh […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Gerrit-Change-Number: 59359 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 18:36:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake, soc/common: Add method to determine the cpu type
by Sridhar Siricilla (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Arthur Heymans, Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59360 ) Change subject: soc/intel/alderlake, soc/common: Add method to determine the cpu type ...................................................................... Patch Set 7: (5 comments) File src/soc/intel/alderlake/cpu.c: https://review.coreboot.org/c/coreboot/+/59360/comment/42561a6f_8ede1b84 PS6, Line 74: 0xBE > could we define an enum for the possible model types ? Ack File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/59360/comment/ad6032df_ead33dc2 PS1, Line 25: return global_cpu_type_bitmask; > > Done […] Ack File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/59360/comment/32d99a8c_06e8c3ca PS6, Line 15: uint8_t > `enum core_type` Ack https://review.coreboot.org/c/coreboot/+/59360/comment/53e108f8_d63f9522 PS6, Line 15: uint8_t __weak get_soc_cpu_type(void) : { : return 0; : } > Should not be necessary to add this weak function, instead let's just make it mandatory for platform […] Agree, when Kconfig option is provided for a feature, it is better to force all dependent functions be implemented. File src/soc/intel/common/block/include/intelblocks/acpi.h: https://review.coreboot.org/c/coreboot/+/59360/comment/f42932a0_69b0aab7 PS6, Line 17: > Since this can return incorrect data before MP-init, then this should have an 'INVALID' or 'UNKNOWN' […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b Gerrit-Change-Number: 59360 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 18:34:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Define soc_get_pcie_rp_type
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59854 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type ...................................................................... soc/intel/alderlake: Define soc_get_pcie_rp_type In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Alder Lake. While we're here, add PCIe RP group definitions for PCH-M chipsets. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/pcie_rp.c 3 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59854/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Gerrit-Change-Number: 59854 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Define soc_get_pcie_rp_type
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59853 to look at the new patch set (#3). Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type ...................................................................... soc/intel/tigerlake: Define soc_get_pcie_rp_type In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Tiger Lake. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 --- M src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/pcie_rp.c 3 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59853/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Gerrit-Change-Number: 59853 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add CPU related APIs
by Sridhar Siricilla (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Tim Wawrzynczak, Sugnan Prabhu S, Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59124 ) Change subject: soc/intel/common: Add CPU related APIs ...................................................................... Patch Set 8: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59124/comment/cafc87a7_2d81962b PS7, Line 13: cpu_get_cpu_typ > `cpu_get_cpu_type` Ack File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/59124/comment/b7cc56f8_6c23566e PS7, Line 34: #define CPUID_PROCESSOR_FREQUENCY 0x16 : : #define CPUID_HYBRID_INFORMATION 0x1a : : /* Structured Extended Feature Flags */ : #define CPUID_STRUCT_EXTENDED_FEATURE_FLAGS 0x7 : #define HYBRID_FEATURE BIT(15) > please use tabs for indentation, and also align the right sides Ack https://review.coreboot.org/c/coreboot/+/59124/comment/5d8a7cf7_976303bf PS7, Line 199: cpu > CPU Ack https://review.coreboot.org/c/coreboot/+/59124/comment/1e866eed_7141833e PS7, Line 199: cpu > CPU Ack https://review.coreboot.org/c/coreboot/+/59124/comment/bdb021a5_ee99c2d7 PS7, Line 212: > nit: extra space Ack https://review.coreboot.org/c/coreboot/+/59124/comment/8912bd27_5deb7b7a PS7, Line 220: core_type > What are the possible return values? 10h(Reserved), 20h(Atom), 30h(Reserved),40h(Core) https://review.coreboot.org/c/coreboot/+/59124/comment/4b503e79_abfd864b PS7, Line 224: cpu_get_bus_frequency > What unit is this in? MHz? It is in MHz. -- To view, visit https://review.coreboot.org/c/coreboot/+/59124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I680f43952ab4abce6e342206688ad32814970a91 Gerrit-Change-Number: 59124 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 18:32:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add CPU related APIs
by Sridhar Siricilla (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Sugnan Prabhu S, Sridhar Siricilla, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Maulik V Vaghela, Sugnan Prabhu S, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59124 to look at the new patch set (#8). Change subject: soc/intel/common: Add CPU related APIs ...................................................................... soc/intel/common: Add CPU related APIs The patch defines below APIs : cpu_is_hybrid_supported() : Check whether CPU is hybrid CPU or not. cpu_get_bus_frequency() : Get CPU's bus frequency in MHz cpu_get_max_non_turbo_ratio() : Get CPU's max non-turbo ratio cpu_get_cpu_type() : Get CPU type. The function must be called if executing CPU is hybrid. TEST=Verified the APIs on the Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I680f43952ab4abce6e342206688ad32814970a91 --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 2 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/59124/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/59124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I680f43952ab4abce6e342206688ad32814970a91 Gerrit-Change-Number: 59124 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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