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Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59808/comment/dbc5cbec_1f628d0a
PS4, Line 12: TEST=Boot on PC Engines apu3
> Very nice! […]
Yes, that's with the serial console enabled and with loglevel 7
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 )
Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59808/comment/780eb174_22346e7c
PS4, Line 12: TEST=Boot on PC Engines apu3
> Boot time went from 2.855s to 2.688s on average, so that's a 167ms improvement. […]
Very nice!
With serial console enabled, I assume?
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Michał Kopeć has submitted this change. ( https://review.coreboot.org/c/gerrit-avatars/+/59833 )
Change subject: 1001940.jpg: add face for mkopec
......................................................................
1001940.jpg: add face for mkopec
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Change-Id: If7a6f8345ef4b2ffb086e35ac0c6e96796cd02bd
---
A 1001940.jpg
1 file changed, 0 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified; Looks good to me, approved
diff --git a/1001940.jpg b/1001940.jpg
new file mode 100644
index 0000000..0a32cbd
--- /dev/null
+++ b/1001940.jpg
Binary files differ
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59870
to look at the new patch set (#5).
Change subject: northbridge/amd/pi/00730F01/northbridge.c: remove unneded global variables
......................................................................
northbridge/amd/pi/00730F01/northbridge.c: remove unneded global variables
Remove global variables `sblink` and `node_nums` and add function
`get_node_nums()` which reads from PCI config once and returns a static
variable.
TEST=Boot Debian 11 on PC Engines apu3
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Change-Id: I20a47f967093ef91355377c164656cabadc30fe6
---
M src/northbridge/amd/pi/00730F01/northbridge.c
1 file changed, 23 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/59870/5
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54754 )
Change subject: cpu/x86/mp_init.c: Fix building with no smihandler
......................................................................
cpu/x86/mp_init.c: Fix building with no smihandler
The build fails because smm_stub_size() tries to find a symbol that
won't be present.
Change-Id: I73fee3cf26c0e37cca03299c6730f7b4f1ef6685
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54754
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/cpu/x86/mp_init.c
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Angel Pons: Looks good to me, approved
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 46cb585..709e7a2 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -1072,6 +1072,9 @@
if (ops->get_cpu_count != NULL)
state->cpu_count = ops->get_cpu_count();
+ if (!is_smm_enabled())
+ return;
+
if (ops->get_smm_info != NULL)
ops->get_smm_info(&state->perm_smbase, &state->perm_smsize,
&state->smm_real_save_state_size);
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 )
Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59808/comment/24e891b9_c3cd124c
PS4, Line 12: TEST=Boot on PC Engines apu3
> Any boottime or log differences?
Boot time went from 2.855s to 2.688s on average, so that's a 167ms improvement. Added to commit message.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59870
to look at the new patch set (#4).
Change subject: northbridge/amd/pi/00730F01/northbridge.c: remove unneded global variables
......................................................................
northbridge/amd/pi/00730F01/northbridge.c: remove unneded global variables
Remove global variables `sblink` and `node_nums` and add function
`get_node_nums()` which reads from PCI config once returns a static variable.
TEST=Boot Debian 11 on PC Engines apu3
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Change-Id: I20a47f967093ef91355377c164656cabadc30fe6
---
M src/northbridge/amd/pi/00730F01/northbridge.c
1 file changed, 23 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/59870/4
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Attention is currently required from: Michał Żygowski, Paul Menzel, Angel Pons, Arthur Heymans.
Hello build bot (Jenkins), Michał Żygowski, Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59808
to look at the new patch set (#11).
Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
northbridge/amd/pi/00730F01: enable PARALLEL_MP
Disable LEGACY_SMP_INIT to enable PARALLEL_MP.
Also remove a large amount of APIC code that is now unnecessary.
TEST=Boot on PC Engines apu3
Boot time reduced from 2.855 seconds to 2.688 seconds average across
5 coldboots.
Inspired by CB:59693
Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/cpu/amd/pi/00730F01/model_16_init.c
M src/northbridge/amd/pi/00730F01/Kconfig
M src/northbridge/amd/pi/00730F01/northbridge.c
3 files changed, 27 insertions(+), 127 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59808/11
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58364 )
Change subject: mb/prodrive/hermes: Correct memory RCOMP settings
......................................................................
mb/prodrive/hermes: Correct memory RCOMP settings
The original RCOMP resistor and target values only apply to ULT CPUs and
do not make sense for the CFL-S CPUs Hermes uses. Fix the RCOMP settings
and the associated comments.
Tested, still boots.
Change-Id: I015797c58c914c6581d472e6d70d2dd7bad2b14f
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58364
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/prodrive/hermes/romstage.c
1 file changed, 4 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/prodrive/hermes/romstage.c b/src/mainboard/prodrive/hermes/romstage.c
index 513bab3..b52c52c 100644
--- a/src/mainboard/prodrive/hermes/romstage.c
+++ b/src/mainboard/prodrive/hermes/romstage.c
@@ -24,11 +24,11 @@
.spd_spec = {.spd_smbus_address = 0xa6}
},
- /* Baseboard uses 121, 81 and 100 rcomp resistors */
- .rcomp_resistor = {121, 81, 100},
+ /* Rcomp resistors on CFL-S are located on the CPU itself */
+ .rcomp_resistor = {121, 75, 100},
- /* Baseboard Rcomp target values. */
- .rcomp_targets = {100, 40, 20, 20, 26},
+ /* Rcomp target values for CFL-S, DDR4 and 2 DIMMs per channel */
+ .rcomp_targets = {60, 26, 20, 20, 26},
/* Baseboard is an interleaved design */
.dq_pins_interleaved = 1,
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