December 2021 - coreboot-gerrit

Change in coreboot[master]: mb/acer/g43t-am3: Add documentation
by Paul Menzel (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Felix Singer, Angel Pons, Michael Büchler. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56838 ) Change subject: mb/acer/g43t-am3: Add documentation ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Can this be submitted? -- To view, visit https://review.coreboot.org/c/coreboot/+/56838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e296b3efbff0260f32badc699f1062f9885fa53 Gerrit-Change-Number: 56838 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Comment-Date: Fri, 03 Dec 2021 16:55:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add check before sending HMRFPO_ENABLE command
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Krishna P Bhat D, Kane Chen, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59698 ) Change subject: soc/intel/common: Add check before sending HMRFPO_ENABLE command ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b Gerrit-Change-Number: 59698 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 16:53:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: Swap TPM I2C with touchscreen I2C
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Chen Wisley, Wisley Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59863 ) Change subject: mb/google/brya/var/redrix: Swap TPM I2C with touchscreen I2C ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a8339c23522019da884944246427512170510b6 Gerrit-Change-Number: 59863 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 16:51:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser
by Felix Held (Code Review) Dec. 3, 2021

Dec. 3, 2021

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59491 ) Change subject: libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser ...................................................................... libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser coreboot stores much information in the CBMEM IMD. Until now it was ignored. This patch makes use of these coreboot tables entries. It also removes get_cbmem_addr() function as it is no longer needed. Moreover, the coreboot tables entry CB_TAG_MRC_CACHE does not exist anymore, as it is not created by the code. It was replaced by CBMEM_ID_MRCDATA entry, so MRCDATA should now be accessible through sysinfo structure field. Change-Id: I5bd02a98ba2631f34014bc0f8e7ebd5a5ddd2321 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59491 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M payloads/libpayload/arch/x86/coreboot.c M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c 4 files changed, 71 insertions(+), 88 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index 38ede87..cad1396 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -47,20 +47,12 @@ info->x86_rom_var_mtrr_index = rom_mtrr->index; } -static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info) -{ - info->mrc_cache = get_cbmem_addr(ptr); -} - int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) { switch(rec->tag) { case CB_TAG_X86_ROM_MTRR: cb_parse_x86_rom_var_mtrr(rec, info); break; - case CB_TAG_MRC_CACHE: - cb_parse_mrc_cache(rec, info); - break; default: return 0; } diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 914cfa5..3fd3fc8 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -321,6 +321,16 @@ uint64_t boot_media_size; }; + +struct cb_cbmem_entry { + uint32_t tag; + uint32_t size; + + uint64_t address; + uint32_t entry_size; + uint32_t id; +}; + struct cb_tsc_info { uint32_t tag; uint32_t size; @@ -443,6 +453,4 @@ (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ + (sizeof((_rec)->map[0]) * (_idx))) -/* Helper functions */ -uintptr_t get_cbmem_addr(const void *cbmem_tab_entry); #endif diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index b34476d..376f298 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -150,6 +150,12 @@ #endif /* USB Type-C Port Configuration Info */ uintptr_t type_c_info; + + /* CBFS RW/RO Metadata Cache */ + uintptr_t cbfs_ro_mcache_offset; + uint32_t cbfs_ro_mcache_size; + uintptr_t cbfs_rw_mcache_offset; + uint32_t cbfs_rw_mcache_size; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index bd10411..79a382b 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -29,6 +29,7 @@ #include <libpayload-config.h> #include <libpayload.h> +#include <commonlib/bsd/cbmem_id.h> #include <coreboot_tables.h> #include <stdint.h> @@ -41,12 +42,6 @@ /* === Parsing code === */ /* This is the generic parsing code. */ -uintptr_t get_cbmem_addr(const void *const cbmem_tab_entry) -{ - const struct cb_cbmem_tab *const cbmem = cbmem_tab_entry; - return cbmem->cbmem_tab; -} - static void cb_parse_memory(void *ptr, struct sysinfo_t *info) { struct cb_memory *mem = ptr; @@ -83,11 +78,6 @@ info->cb_serial = virt_to_phys(ptr); } -static void cb_parse_vboot_workbuf(unsigned char *ptr, struct sysinfo_t *info) -{ - info->vboot_workbuf = get_cbmem_addr(ptr); -} - static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) { struct lb_range *vbnv = (struct lb_range *)ptr; @@ -128,26 +118,6 @@ info->macs[i] = macs->mac_addrs[i]; } -static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) -{ - info->tstamp_table = get_cbmem_addr(ptr); -} - -static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) -{ - info->cbmem_cons = get_cbmem_addr(ptr); -} - -static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) -{ - info->acpi_gnvs = get_cbmem_addr(ptr); -} - -static void cb_parse_acpi_cnvs(unsigned char *ptr, struct sysinfo_t *info) -{ - info->acpi_cnvs = get_cbmem_addr(ptr); -} - static void cb_parse_board_config(unsigned char *ptr, struct sysinfo_t *info) { struct cb_board_config *const config = (struct cb_board_config *)ptr; @@ -188,11 +158,6 @@ *info = virt_to_phys(str->string); } -static void cb_parse_wifi_calibration(void *ptr, struct sysinfo_t *info) -{ - info->wifi_calibration = get_cbmem_addr(ptr); -} - static void cb_parse_ramoops(void *ptr, struct sysinfo_t *info) { struct lb_range *ramoops = (struct lb_range *)ptr; @@ -236,21 +201,6 @@ info->boot_media_size = bmp->boot_media_size; } -static void cb_parse_vpd(void *ptr, struct sysinfo_t *info) -{ - info->chromeos_vpd = get_cbmem_addr(ptr); -} - -static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info) -{ - info->fmap_cache = get_cbmem_addr(ptr); -} - -static void cb_parse_type_c_info(void *ptr, struct sysinfo_t *info) -{ - info->type_c_info = get_cbmem_addr(ptr); -} - #if CONFIG(LP_TIMER_RDTSC) static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info) { @@ -264,6 +214,57 @@ } #endif +static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info) +{ + const struct cb_cbmem_entry *cbmem_entry = ptr; + + if (cbmem_entry->size != sizeof(*cbmem_entry)) + return; + + switch (cbmem_entry->id) { + case CBMEM_ID_ACPI_CNVS: + info->acpi_cnvs = cbmem_entry->address; + break; + case CBMEM_ID_ACPI_GNVS: + info->acpi_gnvs = cbmem_entry->address; + break; + case CBMEM_ID_CBFS_RO_MCACHE: + info->cbfs_ro_mcache_offset = cbmem_entry->address; + info->cbfs_ro_mcache_size = cbmem_entry->size; + break; + case CBMEM_ID_CBFS_RW_MCACHE: + info->cbfs_rw_mcache_offset = cbmem_entry->address; + info->cbfs_rw_mcache_size = cbmem_entry->size; + break; + case CBMEM_ID_CONSOLE: + info->cbmem_cons = cbmem_entry->address; + break; + case CBMEM_ID_MRCDATA: + info->mrc_cache = cbmem_entry->address; + break; + case CBMEM_ID_VBOOT_WORKBUF: + info->vboot_workbuf = cbmem_entry->address; + break; + case CBMEM_ID_TIMESTAMP: + info->tstamp_table = cbmem_entry->address; + break; + case CBMEM_ID_VPD: + info->chromeos_vpd = cbmem_entry->address; + break; + case CBMEM_ID_FMAP: + info->fmap_cache = cbmem_entry->address; + break; + case CBMEM_ID_WIFI_CALIBRATION: + info->wifi_calibration = cbmem_entry->address; + break; + case CBMEM_ID_TYPE_C_INFO: + info->type_c_info = cbmem_entry->address; + break; + default: + break; + } +} + int cb_parse_header(void *addr, int len, struct sysinfo_t *info) { struct cb_header *header; @@ -372,33 +373,15 @@ case CB_TAG_VBNV: cb_parse_vbnv(ptr, info); break; - case CB_TAG_VBOOT_WORKBUF: - cb_parse_vboot_workbuf(ptr, info); - break; case CB_TAG_MAC_ADDRS: cb_parse_mac_addresses(ptr, info); break; case CB_TAG_SERIALNO: cb_parse_string(ptr, &info->serialno); break; - case CB_TAG_TIMESTAMPS: - cb_parse_tstamp(ptr, info); - break; - case CB_TAG_CBMEM_CONSOLE: - cb_parse_cbmem_cons(ptr, info); - break; - case CB_TAG_ACPI_GNVS: - cb_parse_acpi_gnvs(ptr, info); - break; - case CB_TAG_ACPI_CNVS: - cb_parse_acpi_cnvs(ptr, info); - break; case CB_TAG_BOARD_CONFIG: cb_parse_board_config(ptr, info); break; - case CB_TAG_WIFI_CALIBRATION: - cb_parse_wifi_calibration(ptr, info); - break; case CB_TAG_RAM_OOPS: cb_parse_ramoops(ptr, info); break; @@ -414,20 +397,14 @@ case CB_TAG_BOOT_MEDIA_PARAMS: cb_parse_boot_media_params(ptr, info); break; + case CB_TAG_CBMEM_ENTRY: + cb_parse_cbmem_entry(ptr, info); + break; #if CONFIG(LP_TIMER_RDTSC) case CB_TAG_TSC_INFO: cb_parse_tsc_info(ptr, info); break; #endif - case CB_TAG_VPD: - cb_parse_vpd(ptr, info); - break; - case CB_TAG_FMAP: - cb_parse_fmap_cache(ptr, info); - break; - case CB_TAG_TYPE_C_INFO: - cb_parse_type_c_info(ptr, info); - break; default: cb_parse_arch_specific(rec, info); break; 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bd02a98ba2631f34014bc0f8e7ebd5a5ddd2321 Gerrit-Change-Number: 59491 Gerrit-PatchSet: 6 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Generate new SPD ID for new memory parts
by Felix Held (Code Review) Dec. 3, 2021

Dec. 3, 2021

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59642 ) Change subject: mb/google/dedede/var/drawcia: Generate new SPD ID for new memory parts ...................................................................... mb/google/dedede/var/drawcia: Generate new SPD ID for new memory parts Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Samsung K4U6E3S4AA-MGCL BUG=b:204014463 TEST=run part_id_gen to generate SPD id Change-Id: Icb0f211508450b16b2e5d214ae6adc9852718a59 Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59642 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc M src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc index 96284d1..f975bfb 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc @@ -4,4 +4,4 @@ # ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/drawcia/memory src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL, K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt index 78cc95d..8a3c5c8 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt @@ -10,3 +10,4 @@ MT53E512M32D1NP-046 WT:B 0 (0000) H54G46CYRBX267 0 (0000) K4U6E3S4AB-MGCL 0 (0000) +K4U6E3S4AA-MGCL 0 (0000) diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt index f195c25..4a3e217 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt @@ -4,3 +4,4 @@ MT53E512M32D1NP-046 WT:B H54G46CYRBX267 K4U6E3S4AB-MGCL +K4U6E3S4AA-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/59642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb0f211508450b16b2e5d214ae6adc9852718a59 Gerrit-Change-Number: 59642 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Create beadrix variant
by 9elements QA (Code Review) Dec. 3, 2021

Dec. 3, 2021

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59302 ) Change subject: mb/google/dedede: Create beadrix variant ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 1 / 9 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/83157 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/83156 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83155 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/83154 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/83153 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/83152 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83151 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/83150 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/83149 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/59302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie08cbc19967eca8ba31ea3203e71c4e1fef044d6 Gerrit-Change-Number: 59302 Gerrit-PatchSet: 2 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 16:50:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: region: Rename rdev_readat_full to rdev_read_full
by Felix Held (Code Review) Dec. 3, 2021

Dec. 3, 2021

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59820 ) Change subject: region: Rename rdev_readat_full to rdev_read_full ...................................................................... region: Rename rdev_readat_full to rdev_read_full The 'at' part of the name refers to starting to read from a specific offset, so it doesn't make sense for the 'full' version of the function. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I60d595f0cbd161df171eaa4a76c7a00b6377e2b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59820 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/include/commonlib/region.h M src/lib/cbfs.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 5d73d9e..25efcc8 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -163,7 +163,7 @@ * * You must ensure the buffer is large enough to hold the full region_device. */ -static inline ssize_t rdev_readat_full(const struct region_device *rd, void *b) +static inline ssize_t rdev_read_full(const struct region_device *rd, void *b) { return rdev_readat(rd, b, 0, region_device_sz(rd)); } diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 600d259..b4b6eb1 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -316,7 +316,7 @@ { struct cbfs_preload_context *context = arg; - if (rdev_readat_full(&context->rdev, context->buffer) < 0) { + if (rdev_read_full(&context->rdev, context->buffer) < 0) { ERROR("%s(name='%s') readat failed\n", __func__, context->name); return CB_ERR; } -- To view, visit https://review.coreboot.org/c/coreboot/+/59820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60d595f0cbd161df171eaa4a76c7a00b6377e2b0 Gerrit-Change-Number: 59820 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: northbridge/amd/pi/00730F01: enable PARALLEL_MP
by Michał Kopeć (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Michał Żygowski, Paul Menzel, Angel Pons, Arthur Heymans. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 ) Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59808/comment/dbc5cbec_1f628d0a PS4, Line 12: TEST=Boot on PC Engines apu3 > Very nice! […] Yes, that's with the serial console enabled and with loglevel 7 -- To view, visit https://review.coreboot.org/c/coreboot/+/59808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Gerrit-Change-Number: 59808 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 03 Dec 2021 16:26:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: northbridge/amd/pi/00730F01: enable PARALLEL_MP
by Paul Menzel (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Michał Żygowski, Michał Kopeć, Angel Pons, Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 ) Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59808/comment/780eb174_22346e7c PS4, Line 12: TEST=Boot on PC Engines apu3 > Boot time went from 2.855s to 2.688s on average, so that's a 167ms improvement. […] Very nice! With serial console enabled, I assume? -- To view, visit https://review.coreboot.org/c/coreboot/+/59808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Gerrit-Change-Number: 59808 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 03 Dec 2021 16:23:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in gerrit-avatars[master]: 1001940.jpg: add face for mkopec
by Michał Kopeć (Code Review) Dec. 3, 2021

Dec. 3, 2021

Michał Kopeć has submitted this change. ( https://review.coreboot.org/c/gerrit-avatars/+/59833 ) Change subject: 1001940.jpg: add face for mkopec ...................................................................... 1001940.jpg: add face for mkopec Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: If7a6f8345ef4b2ffb086e35ac0c6e96796cd02bd --- A 1001940.jpg 1 file changed, 0 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified; Looks good to me, approved diff --git a/1001940.jpg b/1001940.jpg new file mode 100644 index 0000000..0a32cbd --- /dev/null +++ b/1001940.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/59833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: If7a6f8345ef4b2ffb086e35ac0c6e96796cd02bd Gerrit-Change-Number: 59833 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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