coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/brya: Update camera NVM parameters
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58374 ) Change subject: mb/google/brya: Update camera NVM parameters ...................................................................... mb/google/brya: Update camera NVM parameters Change HID name from INT3499 to PRP0001 along with size and address width. Size decreased from 10K to 2K, address width decreased from 14 to 8. BUG=b:203014972 Test= Boot board and issue commands: `cat /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom > ./brya_imx208_eeprom.bin` `hexdump -C brya_imx208_eeprom.bin > brya_imx208_eeprom_dump.log` You should see the result in brya_imx208_eeprom_dump.log to be same as module nvm file by vendor provided or meet the Intel nvm calibration format. (e.g. first 4 bytes be 0x01, 0x03, 0x01, 0x00) Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58374 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 6812f20..3822a2c 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -522,18 +522,19 @@ end end chip drivers/intel/mipi_camera - register "acpi_hid" = ""INT3499"" + register "acpi_hid" = ""ACPI_DT_NAMESPACE_HID"" register "acpi_uid" = "1" register "acpi_name" = ""NVM1"" register "chip_name" = ""GT24C16S"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC"" + register "nvm_compat" = ""atmel,24c1024"" - register "nvm_size" = "0x2800" + register "nvm_size" = "0x800" register "nvm_pagesize" = "0x01" register "nvm_readonly" = "0x01" - register "nvm_width" = "0x0E" + register "nvm_width" = "0x08" device i2c 50 on probe UFC UFC_MIPI_IMX208 -- To view, visit https://review.coreboot.org/c/coreboot/+/58374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 Gerrit-Change-Number: 58374 Gerrit-PatchSet: 10 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: kiran2.kumar(a)intel.com Gerrit-CC: Bernardo Salvador Perez Priego <bernardospp(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/brask: Enable LAN driver to program MAC
by 9elements QA (Code Review) 03 Dec '21

03 Dec '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59087 ) Change subject: mb/google/brya/var/brask: Enable LAN driver to program MAC ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 9 / 1 / 10 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/83212 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/83211 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83210 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/83209 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/83208 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/83207 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83206 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/83205 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/83204 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/83203 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/59087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732 Gerrit-Change-Number: 59087 Gerrit-PatchSet: 5 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 18:15:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Define soc_get_pcie_rp_type
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59854 ) Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/pcie_rp.c: https://review.coreboot.org/c/coreboot/+/59854/comment/d8757082_0d0d8547 PS1, Line 64: if (is_part_of_group(dev, cpu_rp_groups)) > @Tim, just a point for discussion, ADL-N doesn't have CPU RPs hence should it be like this ? […] Good point, I will modify the groups for M, P and N. -- To view, visit https://review.coreboot.org/c/coreboot/+/59854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Gerrit-Change-Number: 59854 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 18:06:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Define soc_get_pcie_rp_type
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. Hello Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59854 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type ...................................................................... soc/intel/alderlake: Define soc_get_pcie_rp_type In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for alderlake. While we're here, add PCIe RP group definitions for PCH-M chipsets. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/pcie_rp.c 3 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59854/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Gerrit-Change-Number: 59854 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Define soc_get_pcie_rp_type
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59853 to look at the new patch set (#2). Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type ...................................................................... soc/intel/tigerlake: Define soc_get_pcie_rp_type In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for tigerlake. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 --- M src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/pcie_rp.c 3 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59853/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Gerrit-Change-Number: 59853 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: acpi: Add #define for Mutex "no timeout" value
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59851 ) Change subject: acpi: Add #define for Mutex "no timeout" value ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59851/comment/454065b9_0071bd53 PS1, Line 8: > nit: may be just call out why we need this? even if further CL is going to use this macro, still its […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16bc9f3f04dd1e3dc0f3eca3e56377e6f48132b2 Gerrit-Change-Number: 59851 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 17:45:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Add #define for Mutex "no timeout" value
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59851 to look at the new patch set (#2). Change subject: acpi: Add #define for Mutex "no timeout" value ...................................................................... acpi: Add #define for Mutex "no timeout" value Some acpigen code may use mutexes, and it is a common idiom to pass a value for the Timeout field of 0xffff, which is interpreted by OSPM to mean "no timeout". Therefore add a macro for this value. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I16bc9f3f04dd1e3dc0f3eca3e56377e6f48132b2 --- M src/include/acpi/acpigen.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/59851/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16bc9f3f04dd1e3dc0f3eca3e56377e6f48132b2 Gerrit-Change-Number: 59851 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/felwinter: Correct garage wake event
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59861 ) Change subject: mb/google/brya/var/felwinter: Correct garage wake event ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59861/comment/527e4cc2_e1b95ba0 PS1, Line 9: Eject event is high. Set wake event to active high. suggestion, add something like: ``` The polarity of the SCI and the wakeup_event_action for the pen ejection feature were both backwards, and was causing the system to fail to enter sleep states because the event was always asserted. ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/59861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I568e9175c7a66599f7a525c32e4def7a79b55a0a Gerrit-Change-Number: 59861 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 17:44:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake
by Krishna P Bhat D (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Nick Vaccaro, Patrick Rudolph. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59826 ) Change subject: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59826/comment/ae601fad_3220c9c7 PS4, Line 11: > `BUG=b:202143532` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Gerrit-Change-Number: 59826 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 17:41:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake
by Krishna P Bhat D (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Krishna P Bhat D, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59826 to look at the new patch set (#5). Change subject: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake ...................................................................... soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake Check the Alderlake CPU ID to determine if cse sub-paritition update is required or not. BUG=b:202143532 Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/59826/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Gerrit-Change-Number: 59826 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021