coreboot-gerrit December 2021

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Change in coreboot[master]: mb/prodrive/hermes: Configure ALC888 port B Vref
by 9elements QA (Code Review) 03 Dec '21

03 Dec '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58879 ) Change subject: mb/prodrive/hermes: Configure ALC888 port B Vref ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 9 / 1 / 10 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/83290 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/83289 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83288 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/83287 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/83286 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/83285 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83284 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/83283 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/83282 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/83281 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/58879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa11ba9c74f643e94046d4983fbce65dbedd1025 Gerrit-Change-Number: 58879 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 20:30:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Define soc_get_pcie_rp_type
by Subrata Banik (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59854 ) Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/pcie_rp.c: https://review.coreboot.org/c/coreboot/+/59854/comment/01ce61dc_9e0af18c PS3, Line 23: get_adl_cpu_type do you really want to run through this loop https://review.coreboot.org/c/coreboot/+/57151/3/src/soc/intel/alderlake/cp… or Kconfig can also be useful here because we are selecting the PCH type while building SoC layer and such decision can even made while compilation itself? thoughts ? if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) return pch_m_rp_groups; return pch_lp_rp_groups; -- To view, visit https://review.coreboot.org/c/coreboot/+/59854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Gerrit-Change-Number: 59854 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 20:00:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/mmu: Port armv8 MMU to x86_64
by build bot (Jenkins) (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30119 ) Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... Patch Set 18: (3 comments) File src/arch/x86/mmu-ramstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134916): https://review.coreboot.org/c/coreboot/+/30119/comment/addc04eb_a6e6e206 PS18, Line 52: BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, mmu_setup_all_resources, NULL); adding a line without newline at end of file File src/arch/x86/mmu-romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134916): https://review.coreboot.org/c/coreboot/+/30119/comment/eb2a5661_7f4c3fff PS18, Line 87: ROMSTAGE_CBMEM_INIT_HOOK(mmu_hook); adding a line without newline at end of file File src/arch/x86/mmu.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134916): https://review.coreboot.org/c/coreboot/+/30119/comment/b22c88bc_8481f265 PS18, Line 379: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/30119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 30119 Gerrit-PatchSet: 18 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 19:34:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/x86/c_start.S: Add proper x86_64 code
by Felix Singer (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59874 ) Change subject: src/arch/x86/c_start.S: Add proper x86_64 code ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59874/comment/8a6705de_bcd30423 PS1, Line 9: assemlby assem_bl_y -- To view, visit https://review.coreboot.org/c/coreboot/+/59874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9b45f69d0b7534b2faacaad0d099cef2667478 Gerrit-Change-Number: 59874 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 19:34:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/x86/exit_car: Add proper x86_64 code
by Felix Singer (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59873 ) Change subject: src/arch/x86/exit_car: Add proper x86_64 code ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59873/comment/e2e5bda5_2ce5ef61 PS1, Line 9: assemlby assem_bl_y -- To view, visit https://review.coreboot.org/c/coreboot/+/59873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42d1086f1220e44076ccf613244fc3c6d804805b Gerrit-Change-Number: 59873 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 19:33:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/emulation/qemu-i440fx: Fix struct packing
by Felix Singer (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph, Arthur Heymans, Angel Pons. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59872 ) Change subject: src/mainboard/emulation/qemu-i440fx: Fix struct packing ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59872/comment/9c571b2f_7154440a PS1, Line 10: invlid inv_a_lid -- To view, visit https://review.coreboot.org/c/coreboot/+/59872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560 Gerrit-Change-Number: 59872 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 19:32:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/x86/c_start.S: Add proper x86_64 code
by Patrick Rudolph (Code Review) 03 Dec '21

03 Dec '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59874 ) Change subject: src/arch/x86/c_start.S: Add proper x86_64 code ...................................................................... src/arch/x86/c_start.S: Add proper x86_64 code Don't truncate upper bits in assemlby code and thus allow loading of ramstage above 4GiB. Tested on qemu. Change-Id: Ifc9b45f69d0b7534b2faacaad0d099cef2667478 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/c_start.S 1 file changed, 35 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59874/1 diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 9e718fc..c979e81 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -62,6 +62,24 @@ leal _stack, %edi #endif +#if ENV_X86_64 + /** poison the stack. Code should not count on the + * stack being full of zeros. This stack poisoning + * recently uncovered a bug in the broadcast SIPI + * code. + */ + movabs $_estack, %rcx + sub %rdi, %rcx + shr $3, %rcx /* it is 64 bit aligned, right? */ + movq $0xDEADBEEFDEADBEEF, %rax + rep + stosq + + /* Set new stack with enforced alignment. */ + movabs $_estack, %rsp + movq $(~(CONFIG_STACK_SIZE-1)), %rax + and %rax, %rsp +#else /** poison the stack. Code should not count on the * stack being full of zeros. This stack poisoning * recently uncovered a bug in the broadcast SIPI @@ -77,13 +95,23 @@ /* Set new stack with enforced alignment. */ movl $_estack, %esp andl $(~(CONFIG_STACK_SIZE-1)), %esp - +#endif push_cpu_info #if CONFIG(CPU_INFO_V2) /* Allocate the per_cpu_segment_data on the stack */ push_per_cpu_segment_data +#if ENV_X86_64 + /* + * Update the BSP's per_cpu_segment_descriptor to point to the + * per_cpu_segment_data that was allocated on the stack. + */ + set_segment_descriptor_base $per_cpu_segment_descriptors, %esp + + movabs per_cpu_segment_selector, %rax + mov %eax, %gs +#else /* * Update the BSP's per_cpu_segment_descriptor to point to the * per_cpu_segment_data that was allocated on the stack. @@ -93,6 +121,7 @@ mov per_cpu_segment_selector, %eax mov %eax, %gs #endif +#endif /* * Now we are finished. Memory is up, data is copied and @@ -101,7 +130,12 @@ */ post_code(POST_PRE_HARDWAREMAIN) /* post 6e */ +#if ENV_X86_64 + movq $0xFFFFFFFFFFFFFFF0, %rax + and %rax, %rsp +#else andl $0xFFFFFFF0, %esp +#endif #if CONFIG(ASAN_IN_RAMSTAGE) call asan_init -- To view, visit https://review.coreboot.org/c/coreboot/+/59874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9b45f69d0b7534b2faacaad0d099cef2667478 Gerrit-Change-Number: 59874 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes: Add board URL
by 9elements QA (Code Review) 03 Dec '21

03 Dec '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59837 ) Change subject: mb/prodrive/hermes: Add board URL ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 9 / 1 / 10 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/83234 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/83233 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83232 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/83231 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/83230 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/83229 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83228 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/83227 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/83226 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/83225 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/59837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I943d0e2a91778df306f323e2b889cd4e928e0c2b Gerrit-Change-Number: 59837 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 18:47:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/x86/exit_car: Add proper x86_64 code
by Patrick Rudolph (Code Review) 03 Dec '21

03 Dec '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59873 ) Change subject: src/arch/x86/exit_car: Add proper x86_64 code ...................................................................... src/arch/x86/exit_car: Add proper x86_64 code Don't truncate upper bits in assemlby code and thus allow loading of postcar stage above 4GiB. Tested on qemu. Change-Id: I42d1086f1220e44076ccf613244fc3c6d804805b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/exit_car.S 1 file changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/59873/1 diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 9b89ffb..5d1ffdc 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -111,13 +111,20 @@ #if CONFIG(SOC_SETS_MSRS) +#if ENV_X86_64 + mov %rsp, %rbp + + /* Need to align stack to 16 bytes at the call instruction. Therefore + account for the 1 push. */ + movq $0xfffffffffffffff0, %rax + and %rax, %rsp + mov %rbp, %rdi +#else mov %esp, %ebp /* Need to align stack to 16 bytes at the call instruction. Therefore account for the 1 push. */ andl $0xfffffff0, %esp -#if ENV_X86_64 - mov %rbp, %rdi -#else + sub $12, %esp push %ebp #endif @@ -125,10 +132,18 @@ call soc_set_mtrrs /* Ignore fixing up %esp since we're setting it a new value. */ +#if ENV_X86_64 + /* rax: new top_of_stack with setup_stack_and_mtrrs data removed */ + mov %rax, %rsp + /* Align stack to 16 bytes at call instruction. */ + movq $0xfffffffffffffff0, %rax + and %rax, %rsp +#else /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */ movl %eax, %esp /* Align stack to 16 bytes at call instruction. */ andl $0xfffffff0, %esp +#endif call soc_enable_mtrrs #else /* CONFIG_SOC_SETS_MSRS */ /* Clear variable MTRRs. */ @@ -174,8 +189,14 @@ wrmsr #endif /* CONFIG_SOC_SETS_MSRS */ +#if ENV_X86_64 + /* Align stack to 16 bytes at call instruction. */ + movq $0xfffffffffffffff0, %rax + and %rax, %rsp +#else /* Align stack to 16 bytes at call instruction. */ andl $0xfffffff0, %esp +#endif /* Call into main for postcar. */ call main /* Should never return. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42d1086f1220e44076ccf613244fc3c6d804805b Gerrit-Change-Number: 59873 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mainboard/emulation/qemu-i440fx: Fix struct packing
by Patrick Rudolph (Code Review) 03 Dec '21

03 Dec '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59872 ) Change subject: src/mainboard/emulation/qemu-i440fx: Fix struct packing ...................................................................... src/mainboard/emulation/qemu-i440fx: Fix struct packing On x86_64 the struct isn't packed, causing the fw_cfg parser to return invlid memory entries (possible others as well) through fw_cfg. Fix that by packing all structs. Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/59872/1 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index e972f54..817d1a5 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -69,18 +69,18 @@ uint16_t select; /* write this to 0x510 to read it */ uint16_t reserved; char name[FW_CFG_MAX_FILE_PATH]; -} FWCfgFile; +} __packed FWCfgFile; typedef struct FWCfgFiles { uint32_t count; FWCfgFile f[]; -} FWCfgFiles; +} __packed FWCfgFiles; typedef struct FwCfgE820Entry { uint64_t address; uint64_t length; uint32_t type; -} FwCfgE820Entry __attribute((__aligned__(4))); +} __packed FwCfgE820Entry __attribute((__aligned__(4))); #define SMBIOS_FIELD_ENTRY 0 @@ -91,7 +91,7 @@ uint8_t headertype; uint8_t tabletype; uint16_t fieldoffset; -} FwCfgSmbios; +} __packed FwCfgSmbios; /* FW_CFG_ID bits */ #define FW_CFG_VERSION 0x01 @@ -113,6 +113,6 @@ uint32_t control; uint32_t length; uint64_t address; -} FwCfgDmaAccess; +} __packed FwCfgDmaAccess; #endif /* FW_CFG_IF_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560 Gerrit-Change-Number: 59872 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2021