coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratio
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59789 ) Change subject: soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratio ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If73df17faaf7b870ae311460a868d52352683c0c Gerrit-Change-Number: 59789 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 20:47:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add CPU related APIs
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Sugnan Prabhu S, Sridhar Siricilla, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59124 ) Change subject: soc/intel/common: Add CPU related APIs ...................................................................... Patch Set 8: Code-Review+2 (1 comment) File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/59124/comment/df533bbb_3f913564 PS8, Line 210: union cpuid_nat_model_id_and_core_type { : struct { : u32 native_mode_id:24; : u32 core_type:8; : } bits; : u32 hybrid_info; : }; : union cpuid_nat_model_id_and_core_type eax; nit: you don't have to change this, but you don't need the name for the union, e.g. ``` union { struct { u32 native_mode_id:24; u32 core_type:8; } bits; u32 hybrid_info; } eax; eax.hybrid_info = cpuid_eax(...) ``` ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/59124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I680f43952ab4abce6e342206688ad32814970a91 Gerrit-Change-Number: 59124 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 20:46:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Define soc_get_pcie_rp_type
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59854 ) Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/pcie_rp.c: https://review.coreboot.org/c/coreboot/+/59854/comment/cc023ecc_d9e3e0be PS3, Line 23: get_adl_cpu_type > do you really want to run through this loop https://review.coreboot. […] I'll buy that. -- To view, visit https://review.coreboot.org/c/coreboot/+/59854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Gerrit-Change-Number: 59854 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 20:42:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Define soc_get_pcie_rp_type
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59854 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type ...................................................................... soc/intel/alderlake: Define soc_get_pcie_rp_type In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Alder Lake. While we're here, add PCIe RP group definitions for PCH-M chipsets. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/pcie_rp.c 3 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59854/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Gerrit-Change-Number: 59854 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/prodrive/hermes: Configure ALC888 port B Vref
by 9elements QA (Code Review) 03 Dec '21

03 Dec '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58879 ) Change subject: mb/prodrive/hermes: Configure ALC888 port B Vref ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 9 / 1 / 10 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/83290 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/83289 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83288 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/83287 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/83286 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/83285 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83284 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/83283 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/83282 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/83281 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/58879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa11ba9c74f643e94046d4983fbce65dbedd1025 Gerrit-Change-Number: 58879 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 20:30:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Define soc_get_pcie_rp_type
by Subrata Banik (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59854 ) Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/pcie_rp.c: https://review.coreboot.org/c/coreboot/+/59854/comment/01ce61dc_9e0af18c PS3, Line 23: get_adl_cpu_type do you really want to run through this loop https://review.coreboot.org/c/coreboot/+/57151/3/src/soc/intel/alderlake/cp… or Kconfig can also be useful here because we are selecting the PCH type while building SoC layer and such decision can even made while compilation itself? thoughts ? if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) return pch_m_rp_groups; return pch_lp_rp_groups; -- To view, visit https://review.coreboot.org/c/coreboot/+/59854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Gerrit-Change-Number: 59854 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 20:00:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/mmu: Port armv8 MMU to x86_64
by build bot (Jenkins) (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30119 ) Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... Patch Set 18: (3 comments) File src/arch/x86/mmu-ramstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134916): https://review.coreboot.org/c/coreboot/+/30119/comment/addc04eb_a6e6e206 PS18, Line 52: BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, mmu_setup_all_resources, NULL); adding a line without newline at end of file File src/arch/x86/mmu-romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134916): https://review.coreboot.org/c/coreboot/+/30119/comment/eb2a5661_7f4c3fff PS18, Line 87: ROMSTAGE_CBMEM_INIT_HOOK(mmu_hook); adding a line without newline at end of file File src/arch/x86/mmu.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134916): https://review.coreboot.org/c/coreboot/+/30119/comment/b22c88bc_8481f265 PS18, Line 379: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/30119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 30119 Gerrit-PatchSet: 18 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 19:34:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/x86/c_start.S: Add proper x86_64 code
by Felix Singer (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59874 ) Change subject: src/arch/x86/c_start.S: Add proper x86_64 code ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59874/comment/8a6705de_bcd30423 PS1, Line 9: assemlby assem_bl_y -- To view, visit https://review.coreboot.org/c/coreboot/+/59874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9b45f69d0b7534b2faacaad0d099cef2667478 Gerrit-Change-Number: 59874 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 19:34:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/x86/exit_car: Add proper x86_64 code
by Felix Singer (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59873 ) Change subject: src/arch/x86/exit_car: Add proper x86_64 code ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59873/comment/e2e5bda5_2ce5ef61 PS1, Line 9: assemlby assem_bl_y -- To view, visit https://review.coreboot.org/c/coreboot/+/59873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42d1086f1220e44076ccf613244fc3c6d804805b Gerrit-Change-Number: 59873 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 19:33:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/emulation/qemu-i440fx: Fix struct packing
by Felix Singer (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph, Arthur Heymans, Angel Pons. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59872 ) Change subject: src/mainboard/emulation/qemu-i440fx: Fix struct packing ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59872/comment/9c571b2f_7154440a PS1, Line 10: invlid inv_a_lid -- To view, visit https://review.coreboot.org/c/coreboot/+/59872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560 Gerrit-Change-Number: 59872 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 19:32:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021