coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya/var/felwinter: Add WiFi SAR table for felwinter
by Felix Held (Code Review) 03 Dec '21

03 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59718 ) Change subject: mb/google/brya/var/felwinter: Add WiFi SAR table for felwinter ...................................................................... mb/google/brya/var/felwinter: Add WiFi SAR table for felwinter Add WiFi SAR table for felwinter. BUG=b:206901900 TEST=emerge-brya chromeos-config chromeos-config-bsp-private coreboot-private-files-baseboard-brya coreboot chromeos-bootimage and checked SAR table can load by WiFi driver. Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I0de710f4447302ee545a67cbd79373bdd2077637 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59718 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/felwinter/variant.c 2 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index cd00815..ead3348 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -108,6 +108,7 @@ bool "-> Felwinter" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENERIC_GPIO_KEYS + select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_ANAHERA bool "-> Anahera" diff --git a/src/mainboard/google/brya/variants/felwinter/variant.c b/src/mainboard/google/brya/variants/felwinter/variant.c index ee39ef0..8b270de 100644 --- a/src/mainboard/google/brya/variants/felwinter/variant.c +++ b/src/mainboard/google/brya/variants/felwinter/variant.c @@ -3,6 +3,12 @@ #include <chip.h> #include <fw_config.h> #include <baseboard/variants.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { -- To view, visit https://review.coreboot.org/c/coreboot/+/59718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de710f4447302ee545a67cbd79373bdd2077637 Gerrit-Change-Number: 59718 Gerrit-PatchSet: 6 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Define the helper functions
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

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Change in coreboot[master]: soc/intel/tigerlake: Define soc_get_pcie_rp_type
by Subrata Banik (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59853 ) Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/soc/intel/common/block/include/intelblocks/pcie_rp.h: https://review.coreboot.org/c/coreboot/+/59853/comment/b77f7c18_f5ee2104 PS3, Line 120: /*For PCIe RTD3 support, each SoC that uses it must implement this function. */ @Tim, one space after `/*` -- To view, visit https://review.coreboot.org/c/coreboot/+/59853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Gerrit-Change-Number: 59853 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:13:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable CPPCv3
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Paul Menzel, Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59363 ) Change subject: soc/intel/alderlake: Enable CPPCv3 ...................................................................... Patch Set 7: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59363/comment/8d46a37d_2aedec5a PS5, Line 7: for Intel Alderlake > Remove as it’s in the prefix. Done https://review.coreboot.org/c/coreboot/+/59363/comment/ceb324f4_31aa023d PS5, Line 9: Alderlake > Alder Lake Done Commit Message: https://review.coreboot.org/c/coreboot/+/59363/comment/e31681b2_f2de0b3d PS7, Line 12: OS patches link to the patches? -- To view, visit https://review.coreboot.org/c/coreboot/+/59363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaacd4a4ba953d8337f557903ed2ea9da4a60fb9 Gerrit-Change-Number: 59363 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:13:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Add #define for Mutex "no timeout" value
by Subrata Banik (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59851 ) Change subject: acpi: Add #define for Mutex "no timeout" value ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59851/comment/9ae64210_17bb37cb PS1, Line 8: > Done Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/59851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16bc9f3f04dd1e3dc0f3eca3e56377e6f48132b2 Gerrit-Change-Number: 59851 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:12:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Arthur Heymans, Nico Huber, Paul Menzel, Ravindra, Sridhar Siricilla, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 ) Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core ...................................................................... Patch Set 7: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59359/comment/48291d36_0b55bd74 PS7, Line 15: XPPPC `XPPC` File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/59359/comment/71360317_a7402d40 PS7, Line 26: u8 global_cpu_type[MAX_CPU_COUNT]; please don't reach into other modules' data; use an accessor function https://review.coreboot.org/c/coreboot/+/59359/comment/1faaf074_0343345b PS7, Line 62: void __weak get_cpu_scaling_factor(u16 *big_core_scal_factor, u16 *small_core_scal_factor) : { : } : : bool __weak cpu_is_nominal_freq_supported(void) : { : return 0; : } I don't think the weak definitions are necessary; this file is already guarded by the Kconfig SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID, so if an SoC selects that, then it also has to implement these methods as part of that contract. https://review.coreboot.org/c/coreboot/+/59359/comment/c2f0aa52_fabb3d1a PS7, Line 115: 12 `sizeof(scope)` https://review.coreboot.org/c/coreboot/+/59359/comment/56ba0c09_43f7ecc1 PS7, Line 118: 16 `sizeof(scope)` File src/soc/intel/common/block/include/intelblocks/acpi.h: https://review.coreboot.org/c/coreboot/+/59359/comment/7de508d4_b6e10bda PS7, Line 21: /* It gets scaling factor for small and big core */ Since this has to be implemented per-SoC, I'd add a comment that mentions that and also prefix it with `soc_` https://review.coreboot.org/c/coreboot/+/59359/comment/c2bf418f_11ef764c PS7, Line 139: bool cpu_is_nominal_freq_supported(void); Since this has to be implemented per-SoC, I'd add a comment that mentions that and also prefix it with `soc_` -- To view, visit https://review.coreboot.org/c/coreboot/+/59359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Gerrit-Change-Number: 59359 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:11:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpi/acpigen, drivers/tpm: Move definition of set_package_element_op
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Lance Zhao, Sridhar Siricilla. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59729 ) Change subject: acpi/acpigen, drivers/tpm: Move definition of set_package_element_op ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fe70a1f369c97c67bbc1717e6adc7c5f4ba5839 Gerrit-Change-Number: 59729 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:00:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/include/acpi: Move CPPC_PACKAGE_NAME macro definition
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Arthur Heymans, Lance Zhao, Sridhar Siricilla, Michael Niewöhner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59358 ) Change subject: src/include/acpi: Move CPPC_PACKAGE_NAME macro definition ...................................................................... Patch Set 7: Code-Review+2 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59358/comment/9838e4ec_eafcd7e1 PS7, Line 9: The patch move `This patch moves the` https://review.coreboot.org/c/coreboot/+/59358/comment/5a56d6be_b3ca7de0 PS7, Line 10: method get `method will get called from cpu/intel/common in a later patch` Patchset: PS7: c -- To view, visit https://review.coreboot.org/c/coreboot/+/59358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic547445cdbe2b1a3efe44390bd127f577386e7fc Gerrit-Change-Number: 59358 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Fri, 03 Dec 2021 20:59:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake, soc/common: Add method to determine the cpu type
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Arthur Heymans, Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59360 ) Change subject: soc/intel/alderlake, soc/common: Add method to determine the cpu type ...................................................................... Patch Set 7: (4 comments) File src/soc/intel/alderlake/cpu.c: https://review.coreboot.org/c/coreboot/+/59360/comment/413bb621_4c1bda24 PS7, Line 30: ADL_MODEL_P = 0x9A, what about M? File src/soc/intel/common/block/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/59360/comment/c2aa3538_c45255f3 PS7, Line 50: nit: indent two spaces beyond `help` (i.e. one more space here) File src/soc/intel/common/block/include/intelblocks/acpi.h: https://review.coreboot.org/c/coreboot/+/59360/comment/1934139a_b8d50ccc PS7, Line 123: */ I would add more information about this here, e.g. ``` /* * This function determines the type (big or small) of the core that is executing * it and stores the information (in a thread-safe manner) in an array, which * can be consumed after MP initialization is finished. * * It requires the SoC to implement a function `get_soc_cpu_type()` (see below) * which will be called in a critical section to determine the type of the * executing core. */ ``` https://review.coreboot.org/c/coreboot/+/59360/comment/8ad2da4c_3c20a039 PS7, Line 126: /* Returns CPU type (big or small core) */ suggestion: ``` /* * This function returns the core type of the core that it is executing on. It * is designed to be called during MP initialization. If the SoC selects * SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID, then this function must be * implemented, and will be called from set_cpu_type(). */ ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/59360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b Gerrit-Change-Number: 59360 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 20:58:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Define soc_get_pcie_rp_type
by Subrata Banik (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59854 ) Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Gerrit-Change-Number: 59854 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 20:52:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021