coreboot-gerrit December 2021

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Change in coreboot[master]: src/arch/x86/c_start.S: Add proper x86_64 code
by Felix Singer (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59874 ) Change subject: src/arch/x86/c_start.S: Add proper x86_64 code ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59874/comment/8a6705de_bcd30423 PS1, Line 9: assemlby assem_bl_y -- To view, visit https://review.coreboot.org/c/coreboot/+/59874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9b45f69d0b7534b2faacaad0d099cef2667478 Gerrit-Change-Number: 59874 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 19:34:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/x86/exit_car: Add proper x86_64 code
by Felix Singer (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59873 ) Change subject: src/arch/x86/exit_car: Add proper x86_64 code ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59873/comment/e2e5bda5_2ce5ef61 PS1, Line 9: assemlby assem_bl_y -- To view, visit https://review.coreboot.org/c/coreboot/+/59873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42d1086f1220e44076ccf613244fc3c6d804805b Gerrit-Change-Number: 59873 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 19:33:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/emulation/qemu-i440fx: Fix struct packing
by Felix Singer (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph, Arthur Heymans, Angel Pons. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59872 ) Change subject: src/mainboard/emulation/qemu-i440fx: Fix struct packing ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59872/comment/9c571b2f_7154440a PS1, Line 10: invlid inv_a_lid -- To view, visit https://review.coreboot.org/c/coreboot/+/59872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560 Gerrit-Change-Number: 59872 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 19:32:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/x86/c_start.S: Add proper x86_64 code
by Patrick Rudolph (Code Review) 03 Dec '21

03 Dec '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59874 ) Change subject: src/arch/x86/c_start.S: Add proper x86_64 code ...................................................................... src/arch/x86/c_start.S: Add proper x86_64 code Don't truncate upper bits in assemlby code and thus allow loading of ramstage above 4GiB. Tested on qemu. Change-Id: Ifc9b45f69d0b7534b2faacaad0d099cef2667478 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/c_start.S 1 file changed, 35 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59874/1 diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 9e718fc..c979e81 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -62,6 +62,24 @@ leal _stack, %edi #endif +#if ENV_X86_64 + /** poison the stack. Code should not count on the + * stack being full of zeros. This stack poisoning + * recently uncovered a bug in the broadcast SIPI + * code. + */ + movabs $_estack, %rcx + sub %rdi, %rcx + shr $3, %rcx /* it is 64 bit aligned, right? */ + movq $0xDEADBEEFDEADBEEF, %rax + rep + stosq + + /* Set new stack with enforced alignment. */ + movabs $_estack, %rsp + movq $(~(CONFIG_STACK_SIZE-1)), %rax + and %rax, %rsp +#else /** poison the stack. Code should not count on the * stack being full of zeros. This stack poisoning * recently uncovered a bug in the broadcast SIPI @@ -77,13 +95,23 @@ /* Set new stack with enforced alignment. */ movl $_estack, %esp andl $(~(CONFIG_STACK_SIZE-1)), %esp - +#endif push_cpu_info #if CONFIG(CPU_INFO_V2) /* Allocate the per_cpu_segment_data on the stack */ push_per_cpu_segment_data +#if ENV_X86_64 + /* + * Update the BSP's per_cpu_segment_descriptor to point to the + * per_cpu_segment_data that was allocated on the stack. + */ + set_segment_descriptor_base $per_cpu_segment_descriptors, %esp + + movabs per_cpu_segment_selector, %rax + mov %eax, %gs +#else /* * Update the BSP's per_cpu_segment_descriptor to point to the * per_cpu_segment_data that was allocated on the stack. @@ -93,6 +121,7 @@ mov per_cpu_segment_selector, %eax mov %eax, %gs #endif +#endif /* * Now we are finished. Memory is up, data is copied and @@ -101,7 +130,12 @@ */ post_code(POST_PRE_HARDWAREMAIN) /* post 6e */ +#if ENV_X86_64 + movq $0xFFFFFFFFFFFFFFF0, %rax + and %rax, %rsp +#else andl $0xFFFFFFF0, %esp +#endif #if CONFIG(ASAN_IN_RAMSTAGE) call asan_init -- To view, visit https://review.coreboot.org/c/coreboot/+/59874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9b45f69d0b7534b2faacaad0d099cef2667478 Gerrit-Change-Number: 59874 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes: Add board URL
by 9elements QA (Code Review) 03 Dec '21

03 Dec '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59837 ) Change subject: mb/prodrive/hermes: Add board URL ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 9 / 1 / 10 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/83234 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/83233 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83232 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/83231 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/83230 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/83229 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83228 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/83227 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/83226 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/83225 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/59837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I943d0e2a91778df306f323e2b889cd4e928e0c2b Gerrit-Change-Number: 59837 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 18:47:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/x86/exit_car: Add proper x86_64 code
by Patrick Rudolph (Code Review) 03 Dec '21

03 Dec '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59873 ) Change subject: src/arch/x86/exit_car: Add proper x86_64 code ...................................................................... src/arch/x86/exit_car: Add proper x86_64 code Don't truncate upper bits in assemlby code and thus allow loading of postcar stage above 4GiB. Tested on qemu. Change-Id: I42d1086f1220e44076ccf613244fc3c6d804805b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/exit_car.S 1 file changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/59873/1 diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 9b89ffb..5d1ffdc 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -111,13 +111,20 @@ #if CONFIG(SOC_SETS_MSRS) +#if ENV_X86_64 + mov %rsp, %rbp + + /* Need to align stack to 16 bytes at the call instruction. Therefore + account for the 1 push. */ + movq $0xfffffffffffffff0, %rax + and %rax, %rsp + mov %rbp, %rdi +#else mov %esp, %ebp /* Need to align stack to 16 bytes at the call instruction. Therefore account for the 1 push. */ andl $0xfffffff0, %esp -#if ENV_X86_64 - mov %rbp, %rdi -#else + sub $12, %esp push %ebp #endif @@ -125,10 +132,18 @@ call soc_set_mtrrs /* Ignore fixing up %esp since we're setting it a new value. */ +#if ENV_X86_64 + /* rax: new top_of_stack with setup_stack_and_mtrrs data removed */ + mov %rax, %rsp + /* Align stack to 16 bytes at call instruction. */ + movq $0xfffffffffffffff0, %rax + and %rax, %rsp +#else /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */ movl %eax, %esp /* Align stack to 16 bytes at call instruction. */ andl $0xfffffff0, %esp +#endif call soc_enable_mtrrs #else /* CONFIG_SOC_SETS_MSRS */ /* Clear variable MTRRs. */ @@ -174,8 +189,14 @@ wrmsr #endif /* CONFIG_SOC_SETS_MSRS */ +#if ENV_X86_64 + /* Align stack to 16 bytes at call instruction. */ + movq $0xfffffffffffffff0, %rax + and %rax, %rsp +#else /* Align stack to 16 bytes at call instruction. */ andl $0xfffffff0, %esp +#endif /* Call into main for postcar. */ call main /* Should never return. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42d1086f1220e44076ccf613244fc3c6d804805b Gerrit-Change-Number: 59873 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mainboard/emulation/qemu-i440fx: Fix struct packing
by Patrick Rudolph (Code Review) 03 Dec '21

03 Dec '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59872 ) Change subject: src/mainboard/emulation/qemu-i440fx: Fix struct packing ...................................................................... src/mainboard/emulation/qemu-i440fx: Fix struct packing On x86_64 the struct isn't packed, causing the fw_cfg parser to return invlid memory entries (possible others as well) through fw_cfg. Fix that by packing all structs. Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/59872/1 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index e972f54..817d1a5 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -69,18 +69,18 @@ uint16_t select; /* write this to 0x510 to read it */ uint16_t reserved; char name[FW_CFG_MAX_FILE_PATH]; -} FWCfgFile; +} __packed FWCfgFile; typedef struct FWCfgFiles { uint32_t count; FWCfgFile f[]; -} FWCfgFiles; +} __packed FWCfgFiles; typedef struct FwCfgE820Entry { uint64_t address; uint64_t length; uint32_t type; -} FwCfgE820Entry __attribute((__aligned__(4))); +} __packed FwCfgE820Entry __attribute((__aligned__(4))); #define SMBIOS_FIELD_ENTRY 0 @@ -91,7 +91,7 @@ uint8_t headertype; uint8_t tabletype; uint16_t fieldoffset; -} FwCfgSmbios; +} __packed FwCfgSmbios; /* FW_CFG_ID bits */ #define FW_CFG_VERSION 0x01 @@ -113,6 +113,6 @@ uint32_t control; uint32_t length; uint64_t address; -} FwCfgDmaAccess; +} __packed FwCfgDmaAccess; #endif /* FW_CFG_IF_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560 Gerrit-Change-Number: 59872 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/arch/x86/exit_car: Fix regression on x86_64
by Patrick Rudolph (Code Review) 03 Dec '21

03 Dec '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59871 ) Change subject: src/arch/x86/exit_car: Fix regression on x86_64 ...................................................................... src/arch/x86/exit_car: Fix regression on x86_64 The commit d023909b "treewide: Disable R_AMD64_32S relocation support" introduced clflush cbmem_top() instead of _cbmem_top_ptr, which isn't intended. Fix that by providing the correct address to clflush. Change-Id: If74591e7753cd9c3c097516430a212d416f53e4d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/exit_car.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/59871/1 diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 527a3cb..9b89ffb 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -62,7 +62,7 @@ btl $CPUID_FEATURE_CLFLUSH_BIT, %edx jnc skip_clflush #if ENV_X86_64 - movabs _cbmem_top_ptr, %rax + movabs $_cbmem_top_ptr, %rax clflush (%rax) #else clflush _cbmem_top_ptr -- To view, visit https://review.coreboot.org/c/coreboot/+/59871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74591e7753cd9c3c097516430a212d416f53e4d Gerrit-Change-Number: 59871 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/mmu: Port armv8 MMU to x86_64
by Patrick Rudolph (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. Patrick Rudolph has uploaded a new patch set (#18) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30119 ) Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... arch/x86/mmu: Port armv8 MMU to x86_64 Add functions to set up page tables for long mode. In addition generate new page tables where necessary: - before CBMEM setup, if CBMEM is above 4GiB - after CBMEM setup, if CBMEM is above 4GiB - at end of BS_DEV_RESOURCES in CBMEM At end of BS_DEV_RESOURCES the memory map is fully known and the page tables can be properly generated based on the memory resources. This allows the CPU to access all DRAM and MMIO even beyond 4GiB. Right now there's no use case for this, but the code is necessary to: - Load stages above 4GiB - Load payloads above 4GiB - Install tables (like CBMEM/ACPI/SMBIOS) above 4GiB - allow coreboot PCI drivers to access BARs mapped above 4GiB Tested on prodrive/hermes: Still boots to payload. Doesn't affect existing x86_32 code. Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/Makefile.inc A src/arch/x86/include/arch/mmu.h A src/arch/x86/mmu-ramstage.c A src/arch/x86/mmu-romstage.c A src/arch/x86/mmu.c M src/commonlib/include/commonlib/cbmem_id.h M src/lib/imd_cbmem.c 7 files changed, 630 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30119/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/30119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 30119 Gerrit-PatchSet: 18 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
by Sridhar Siricilla (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Arthur Heymans, Nico Huber, Paul Menzel, Tim Wawrzynczak, Ravindra, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 ) Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/59359/comment/cfa07ca2_09431bd2 PS3, Line 152: acpigen_write_dword(core_id); > Correct, I have updated the patch that doesn't use bitmask. Ack https://review.coreboot.org/c/coreboot/+/59359/comment/3aecb99d_aec54760 PS3, Line 98: void acpi_write_xppc_method(int core_id) : { : struct cpu_hybrid cpu_hybrid_info; : : acpi_get_cpu_hybrid_info(&cpu_hybrid_info); : acpigen_write_method(XPPC_PACKAGE_NAME, 1); : : if (cpu_is_nominal_freq_supported()) { : : /* : * If Nominal Frequency is supported, update Nominal Frequency and set core's : * Nominal Performance to a scaling factor which depends on core type(big or : * small). : */ : acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 22, : cpu_hybrid_info.nominal_freq); : : /* LOCAL2_OP = (CORE >> core_id) & 1 */ : acpigen_emit_byte(SHIFT_RIGHT_OP); : acpigen_write_integer(cpu_hybrid_info.type_mask); : acpigen_emit_byte(ARG0_OP); : acpigen_emit_byte(LOCAL1_OP); : acpigen_write_and(LOCAL1_OP, ONE_OP, LOCAL2_OP); : : /* : * If core id is big Core, then set big core's scaling factor : * to core's nominal frequency otherwise set small core's scaling factor. : */ : acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); : acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 3, : cpu_hybrid_info.big_core_nom_perf); : acpigen_write_else(); : acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 3, : cpu_hybrid_info.small_core_nom_perf); : acpigen_pop_len(); : } : : acpigen_emit_byte(RETURN_OP); : acpigen_emit_namestring(CPPC_PACKAGE_NAME); : acpigen_pop_len(); : } : : void acpigen_write_CPPC_hybrid_method(int core_id) : { : char scope[16]; : : if (core_id == 0) : snprintf(scope, 12, XPPC_PACKAGE_NAME, 0); : else : snprintf(scope, 16, CONFIG_ACPI_CPU_STRING "." XPPC_PACKAGE_NAME, 0); : : acpigen_write_method("_CPC", 0); : acpigen_emit_byte(RETURN_OP); : acpigen_emit_namestring(scope); : acpigen_write_dword(core_id); : acpigen_pop_len(); > >Each CPU has _CPC method and they all use the implementation called XPPC_PACKAGE_NAME of CPU0? Migh […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Gerrit-Change-Number: 59359 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 18:36:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2021