Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59874 )
Change subject: src/arch/x86/c_start.S: Add proper x86_64 code
......................................................................
src/arch/x86/c_start.S: Add proper x86_64 code
Don't truncate upper bits in assemlby code and thus allow loading
of ramstage above 4GiB. Tested on qemu.
Change-Id: Ifc9b45f69d0b7534b2faacaad0d099cef2667478
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/arch/x86/c_start.S
1 file changed, 35 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59874/1
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 9e718fc..c979e81 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -62,6 +62,24 @@
leal _stack, %edi
#endif
+#if ENV_X86_64
+ /** poison the stack. Code should not count on the
+ * stack being full of zeros. This stack poisoning
+ * recently uncovered a bug in the broadcast SIPI
+ * code.
+ */
+ movabs $_estack, %rcx
+ sub %rdi, %rcx
+ shr $3, %rcx /* it is 64 bit aligned, right? */
+ movq $0xDEADBEEFDEADBEEF, %rax
+ rep
+ stosq
+
+ /* Set new stack with enforced alignment. */
+ movabs $_estack, %rsp
+ movq $(~(CONFIG_STACK_SIZE-1)), %rax
+ and %rax, %rsp
+#else
/** poison the stack. Code should not count on the
* stack being full of zeros. This stack poisoning
* recently uncovered a bug in the broadcast SIPI
@@ -77,13 +95,23 @@
/* Set new stack with enforced alignment. */
movl $_estack, %esp
andl $(~(CONFIG_STACK_SIZE-1)), %esp
-
+#endif
push_cpu_info
#if CONFIG(CPU_INFO_V2)
/* Allocate the per_cpu_segment_data on the stack */
push_per_cpu_segment_data
+#if ENV_X86_64
+ /*
+ * Update the BSP's per_cpu_segment_descriptor to point to the
+ * per_cpu_segment_data that was allocated on the stack.
+ */
+ set_segment_descriptor_base $per_cpu_segment_descriptors, %esp
+
+ movabs per_cpu_segment_selector, %rax
+ mov %eax, %gs
+#else
/*
* Update the BSP's per_cpu_segment_descriptor to point to the
* per_cpu_segment_data that was allocated on the stack.
@@ -93,6 +121,7 @@
mov per_cpu_segment_selector, %eax
mov %eax, %gs
#endif
+#endif
/*
* Now we are finished. Memory is up, data is copied and
@@ -101,7 +130,12 @@
*/
post_code(POST_PRE_HARDWAREMAIN) /* post 6e */
+#if ENV_X86_64
+ movq $0xFFFFFFFFFFFFFFF0, %rax
+ and %rax, %rsp
+#else
andl $0xFFFFFFF0, %esp
+#endif
#if CONFIG(ASAN_IN_RAMSTAGE)
call asan_init
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ifc9b45f69d0b7534b2faacaad0d099cef2667478
Gerrit-Change-Number: 59874
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
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Attention is currently required from: Patrick Rudolph.
Patrick Rudolph has uploaded a new patch set (#18) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30119 )
Change subject: arch/x86/mmu: Port armv8 MMU to x86_64
......................................................................
arch/x86/mmu: Port armv8 MMU to x86_64
Add functions to set up page tables for long mode.
In addition generate new page tables where necessary:
- before CBMEM setup, if CBMEM is above 4GiB
- after CBMEM setup, if CBMEM is above 4GiB
- at end of BS_DEV_RESOURCES in CBMEM
At end of BS_DEV_RESOURCES the memory map is fully known and the
page tables can be properly generated based on the memory resources.
This allows the CPU to access all DRAM and MMIO even beyond 4GiB.
Right now there's no use case for this, but the code is necessary to:
- Load stages above 4GiB
- Load payloads above 4GiB
- Install tables (like CBMEM/ACPI/SMBIOS) above 4GiB
- allow coreboot PCI drivers to access BARs mapped above 4GiB
Tested on prodrive/hermes: Still boots to payload.
Doesn't affect existing x86_32 code.
Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/arch/x86/Makefile.inc
A src/arch/x86/include/arch/mmu.h
A src/arch/x86/mmu-ramstage.c
A src/arch/x86/mmu-romstage.c
A src/arch/x86/mmu.c
M src/commonlib/include/commonlib/cbmem_id.h
M src/lib/imd_cbmem.c
7 files changed, 630 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30119/18
--
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59360 )
Change subject: soc/intel/alderlake, soc/common: Add method to determine the cpu type
......................................................................
Patch Set 7:
(5 comments)
File src/soc/intel/alderlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/59360/comment/42561a6f_8ede1b84
PS6, Line 74: 0xBE
> could we define an enum for the possible model types ?
Ack
File src/soc/intel/common/block/acpi/cpu_hybrid.c:
https://review.coreboot.org/c/coreboot/+/59360/comment/ad6032df_ead33dc2
PS1, Line 25: return global_cpu_type_bitmask;
> > Done […]
Ack
File src/soc/intel/common/block/acpi/cpu_hybrid.c:
https://review.coreboot.org/c/coreboot/+/59360/comment/32d99a8c_06e8c3ca
PS6, Line 15: uint8_t
> `enum core_type`
Ack
https://review.coreboot.org/c/coreboot/+/59360/comment/53e108f8_d63f9522
PS6, Line 15: uint8_t __weak get_soc_cpu_type(void)
: {
: return 0;
: }
> Should not be necessary to add this weak function, instead let's just make it mandatory for platform […]
Agree, when Kconfig option is provided for a feature, it is better to force all dependent functions be implemented.
File src/soc/intel/common/block/include/intelblocks/acpi.h:
https://review.coreboot.org/c/coreboot/+/59360/comment/f42932a0_69b0aab7
PS6, Line 17:
> Since this can return incorrect data before MP-init, then this should have an 'INVALID' or 'UNKNOWN' […]
Ack
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Attention is currently required from: Subrata Banik, Patrick Rudolph.
Hello build bot (Jenkins), Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59854
to look at the new patch set (#3).
Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type
......................................................................
soc/intel/alderlake: Define soc_get_pcie_rp_type
In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Alder Lake. While we're
here, add PCIe RP group definitions for PCH-M chipsets.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I7438513e10b7cea8dac678b97a901b710247c188
---
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/pcie_rp.c
3 files changed, 54 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59854/3
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Hello build bot (Jenkins), Paul Menzel, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59853
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type
......................................................................
soc/intel/tigerlake: Define soc_get_pcie_rp_type
In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Tiger Lake.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620
---
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
M src/soc/intel/tigerlake/Makefile.inc
A src/soc/intel/tigerlake/pcie_rp.c
3 files changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59853/3
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