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Change subject: soc/intel/alderlake: Implement function to map physical port to EC port
......................................................................
Patch Set 12: Code-Review+1
(1 comment)
File src/soc/intel/alderlake/retimer.c:
https://review.coreboot.org/c/coreboot/+/59666/comment/d37a447d_14353142
PS12, Line 8: uint8_t
so then maybe this should have a different return type
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Change subject: soc/intel/alderlake: Implement function to map physical port to EC port
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Patch Set 12:
(1 comment)
File src/soc/intel/alderlake/retimer.c:
https://review.coreboot.org/c/coreboot/+/59666/comment/446678fb_3aca6607
PS9, Line 30: die("Couldn't find correct port mapping or Invalid input port\n");
I don't think we need to call die() here, returning some kind of error code is probably better (and then printing an error message at the caller).
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Change subject: drivers/intel/usb4/retimer: Add function to correct EC port mapping
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Patch Set 8: Code-Review+2
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Change subject: soc/intel/alderlake: Add support for ADL-N CPU Type
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/soc/intel/alderlake/cpu.c:
PS3:
For another patch: do we still need this function? Or should we rely on the Kconfigs, e.g. SOC_INTEL_ALDERLAKE_PCH_M / PCH_N / PCH_M, etc. ?
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Change subject: soc/intel/alderlake: Define the helper functions
......................................................................
Patch Set 7:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59362/comment/faf1b5e7_195d5e16
PS7, Line 7: the helper functions
`Define CPPCv3 hybrid helper functions`
https://review.coreboot.org/c/coreboot/+/59362/comment/dff765c5_b70dfc8f
PS7, Line 9: defines following
`defines the following`
https://review.coreboot.org/c/coreboot/+/59362/comment/5dee461c_3ba9ca19
PS7, Line 12: TRUE
`true`
https://review.coreboot.org/c/coreboot/+/59362/comment/0bd8cbd1_d83956d7
PS7, Line 13: FASLE
`false`
Patchset:
PS7:
could possibly be squashed with next patch?
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Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/59853/comment/b77f7c18_f5ee2104
PS3, Line 120: /*For PCIe RTD3 support, each SoC that uses it must implement this function. */
@Tim, one space after `/*`
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Change subject: soc/intel/alderlake: Enable CPPCv3
......................................................................
Patch Set 7:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59363/comment/8d46a37d_2aedec5a
PS5, Line 7: for Intel Alderlake
> Remove as it’s in the prefix.
Done
https://review.coreboot.org/c/coreboot/+/59363/comment/ceb324f4_31aa023d
PS5, Line 9: Alderlake
> Alder Lake
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/59363/comment/e31681b2_f2de0b3d
PS7, Line 12: OS patches
link to the patches?
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