coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

1 participants
5518 discussions

Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64)
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Subrata Banik, Wonkyu Kim, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Tim Chu, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59744 ) Change subject: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64) ...................................................................... Patch Set 7: (2 comments) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/59744/comment/50354ec7_59b60d97 PS6, Line 41: uint64_t > > it looks only address related parameters are changed to 64bit. […] I agree with Arthur here, explicit is better with ABIs. File src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/59744/comment/a3c416fc_698a818a PS7, Line 192: Note: This ought to be VOID*, but that won't allow calling this binary on x86_64. > not up to date anymore ;-) 🎉 -- To view, visit https://review.coreboot.org/c/coreboot/+/59744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If12b63a282c660da6f57fe23b0b848e2d155853f Gerrit-Change-Number: 59744 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:41:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Define soc_get_pcie_rp_type
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59853 ) Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/include/intelblocks/pcie_rp.h: https://review.coreboot.org/c/coreboot/+/59853/comment/56d2d530_18782b14 PS3, Line 120: /*For PCIe RTD3 support, each SoC that uses it must implement this function. */ > @Tim, one space after `/*` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Gerrit-Change-Number: 59853 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:37:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Define soc_get_pcie_rp_type
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59853 to look at the new patch set (#4). Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type ...................................................................... soc/intel/tigerlake: Define soc_get_pcie_rp_type In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Tiger Lake. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 --- M src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/pcie_rp.c 3 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59853/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Gerrit-Change-Number: 59853 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Define soc_get_pcie_rp_type
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59854 to look at the new patch set (#5). Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type ...................................................................... soc/intel/alderlake: Define soc_get_pcie_rp_type In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Alder Lake. While we're here, add PCIe RP group definitions for PCH-M chipsets. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/pcie_rp.c 3 files changed, 62 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59854/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Gerrit-Change-Number: 59854 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Add ADL-P 682 (28W) VR config
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Paul Menzel, Curtis Chen, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59736 ) Change subject: soc/intel/alderlake: Add ADL-P 682 (28W) VR config ...................................................................... Patch Set 2: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59736/comment/12617926_a3ccd4f3 PS2, Line 7: 682 nit: `6+8+2` https://review.coreboot.org/c/coreboot/+/59736/comment/1712321f_f5467648 PS2, Line 9: 682 nit: `6+8+2` https://review.coreboot.org/c/coreboot/+/59736/comment/bf09e9f1_b817b481 PS2, Line 10: 682 nit: `6+8+2` File src/soc/intel/alderlake/vr_config.c: https://review.coreboot.org/c/coreboot/+/59736/comment/27e99f5c_2a138b7a PS2, Line 53: 682 nit: `6+8+2` also space after `(` -- To view, visit https://review.coreboot.org/c/coreboot/+/59736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b Gerrit-Change-Number: 59736 Gerrit-PatchSet: 2 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:31:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/gimble: Configure Acoustic noise mitigation
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: YH Lin, Paul Menzel, Anfernee Chen, Mark Hsieh, Zhuohao Lee, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59535 ) Change subject: mb/google/brya/var/gimble: Configure Acoustic noise mitigation ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59535/comment/f46eba4c_96f8bb5f PS1, Line 14: without error. I assume this also reduces audible noise? 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/59535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be3d30403284b98276c837adefd91aa62c971e4 Gerrit-Change-Number: 59535 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:30:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/gimble: Configure Acoustic noise mitigation
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: YH Lin, Paul Menzel, Anfernee Chen, Mark Hsieh, Zhuohao Lee, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59535 ) Change subject: mb/google/brya/var/gimble: Configure Acoustic noise mitigation ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59535/comment/df97992f_f7ed86f4 PS1, Line 10: - Set slow slew rate VCCIA and VCCGT to 16 > Hi Paul, […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be3d30403284b98276c837adefd91aa62c971e4 Gerrit-Change-Number: 59535 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:30:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Comment-In-Reply-To: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Add support for ADL-N PCH
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59752 ) Change subject: soc/intel/alderlake: Add support for ADL-N PCH ...................................................................... soc/intel/alderlake: Add support for ADL-N PCH Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to specify the correct amount of PCIe I/O. Document number 645550 indicates that Alder Lake-N has 12 PCH root ports and no CPU root ports. Document number 645548 indicates ADL-N has 5 clock sources and 5 clock request signals. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/include/soc/bootblock.h 2 files changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Felix Singer: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Kangheui Won: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 2f8f3da..9fe2668 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -11,6 +11,12 @@ help Choose this option if your mainboard has a PCH-M chipset. +config SOC_INTEL_ALDERLAKE_PCH_N + bool + select SOC_INTEL_ALDERLAKE + help + Choose this option if your mainboard has a PCH-N chipset. + config SOC_INTEL_ALDERLAKE_PCH_P bool select SOC_INTEL_ALDERLAKE @@ -178,11 +184,13 @@ config MAX_PCH_ROOT_PORTS int default 10 if SOC_INTEL_ALDERLAKE_PCH_M + default 12 if SOC_INTEL_ALDERLAKE_PCH_N default 12 if SOC_INTEL_ALDERLAKE_PCH_P config MAX_CPU_ROOT_PORTS int default 1 if SOC_INTEL_ALDERLAKE_PCH_M + default 0 if SOC_INTEL_ALDERLAKE_PCH_N default 3 if SOC_INTEL_ALDERLAKE_PCH_P config MAX_ROOT_PORTS @@ -192,11 +200,13 @@ config MAX_PCIE_CLOCK_SRC int default 6 if SOC_INTEL_ALDERLAKE_PCH_M + default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 7 if SOC_INTEL_ALDERLAKE_PCH_P config MAX_PCIE_CLOCK_REQ int default 6 if SOC_INTEL_ALDERLAKE_PCH_M + default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 10 if SOC_INTEL_ALDERLAKE_PCH_P config SMM_TSEG_SIZE diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h index 059568d..ce2e42e 100644 --- a/src/soc/intel/alderlake/include/soc/bootblock.h +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -4,6 +4,7 @@ #define _SOC_ALDERLAKE_BOOTBLOCK_H_ #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \ + CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + \ CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1 #error "Please select exactly one PCH type" #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904 Gerrit-Change-Number: 59752 Gerrit-PatchSet: 10 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/var/gimble: Set PsysPmax to 143 W
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Chia-Ling Hou, Paul Menzel. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59797 ) Change subject: mb/var/gimble: Set PsysPmax to 143 W ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6a203f05ecfcc1020a422850d35fa3fa64e01d0 Gerrit-Change-Number: 59797 Gerrit-PatchSet: 2 Gerrit-Owner: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:29:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP] drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_...
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Anil Kumar K, Paul Menzel, Andrey Petrov, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59638 ) Change subject: [WIP] drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2 ...................................................................... Patch Set 17: (1 comment) File src/drivers/intel/fsp2_0/hand_off_block.c: https://review.coreboot.org/c/coreboot/+/59638/comment/3c81995b_ff5bd49c PS17, Line 326: } BTW, this won't compile right now if you enable the Kconfig, because in this path, if hob_walker.hob is NULL, then it doesn't have a return path. -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 17 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:28:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2021