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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59744 )
Change subject: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64)
......................................................................
Patch Set 7:
(2 comments)
File src/drivers/intel/fsp2_0/include/fsp/info_header.h:
https://review.coreboot.org/c/coreboot/+/59744/comment/50354ec7_59b60d97
PS6, Line 41: uint64_t
> > it looks only address related parameters are changed to 64bit. […]
I agree with Arthur here, explicit is better with ABIs.
File src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h:
https://review.coreboot.org/c/coreboot/+/59744/comment/a3c416fc_698a818a
PS7, Line 192: Note: This ought to be VOID*, but that won't allow calling this binary on x86_64.
> not up to date anymore ;-)
🎉
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Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/59853/comment/56d2d530_18782b14
PS3, Line 120: /*For PCIe RTD3 support, each SoC that uses it must implement this function. */
> @Tim, one space after `/*`
Done
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Hello build bot (Jenkins), Paul Menzel, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type
......................................................................
soc/intel/tigerlake: Define soc_get_pcie_rp_type
In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Tiger Lake.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620
---
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
M src/soc/intel/tigerlake/Makefile.inc
A src/soc/intel/tigerlake/pcie_rp.c
3 files changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59853/4
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Hello build bot (Jenkins), Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type
......................................................................
soc/intel/alderlake: Define soc_get_pcie_rp_type
In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Alder Lake. While we're
here, add PCIe RP group definitions for PCH-M chipsets.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I7438513e10b7cea8dac678b97a901b710247c188
---
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/pcie_rp.c
3 files changed, 62 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59854/5
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Change subject: mb/google/brya/var/gimble: Configure Acoustic noise mitigation
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59535/comment/f46eba4c_96f8bb5f
PS1, Line 14: without error.
I assume this also reduces audible noise? 😊
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Change subject: mb/google/brya/var/gimble: Configure Acoustic noise mitigation
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59535/comment/df97992f_f7ed86f4
PS1, Line 10: - Set slow slew rate VCCIA and VCCGT to 16
> Hi Paul, […]
Done
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Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59752 )
Change subject: soc/intel/alderlake: Add support for ADL-N PCH
......................................................................
soc/intel/alderlake: Add support for ADL-N PCH
Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to
specify the correct amount of PCIe I/O.
Document number 645550 indicates that Alder Lake-N has 12 PCH root ports
and no CPU root ports.
Document number 645548 indicates ADL-N has 5 clock sources and 5 clock
request signals.
Signed-off-by: Usha P <usha.p(a)intel.com>
Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/include/soc/bootblock.h
2 files changed, 11 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
Felix Singer: Looks good to me, but someone else must approve
Tim Wawrzynczak: Looks good to me, approved
Kangheui Won: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 2f8f3da..9fe2668 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -11,6 +11,12 @@
help
Choose this option if your mainboard has a PCH-M chipset.
+config SOC_INTEL_ALDERLAKE_PCH_N
+ bool
+ select SOC_INTEL_ALDERLAKE
+ help
+ Choose this option if your mainboard has a PCH-N chipset.
+
config SOC_INTEL_ALDERLAKE_PCH_P
bool
select SOC_INTEL_ALDERLAKE
@@ -178,11 +184,13 @@
config MAX_PCH_ROOT_PORTS
int
default 10 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 12 if SOC_INTEL_ALDERLAKE_PCH_N
default 12 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_CPU_ROOT_PORTS
int
default 1 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 0 if SOC_INTEL_ALDERLAKE_PCH_N
default 3 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_ROOT_PORTS
@@ -192,11 +200,13 @@
config MAX_PCIE_CLOCK_SRC
int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 5 if SOC_INTEL_ALDERLAKE_PCH_N
default 7 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_PCIE_CLOCK_REQ
int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 5 if SOC_INTEL_ALDERLAKE_PCH_N
default 10 if SOC_INTEL_ALDERLAKE_PCH_P
config SMM_TSEG_SIZE
diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h
index 059568d..ce2e42e 100644
--- a/src/soc/intel/alderlake/include/soc/bootblock.h
+++ b/src/soc/intel/alderlake/include/soc/bootblock.h
@@ -4,6 +4,7 @@
#define _SOC_ALDERLAKE_BOOTBLOCK_H_
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \
+ CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + \
CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1
#error "Please select exactly one PCH type"
#endif
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Change subject: mb/var/gimble: Set PsysPmax to 143 W
......................................................................
Patch Set 2: Code-Review+2
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Change subject: [WIP] drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
......................................................................
Patch Set 17:
(1 comment)
File src/drivers/intel/fsp2_0/hand_off_block.c:
https://review.coreboot.org/c/coreboot/+/59638/comment/3c81995b_ff5bd49c
PS17, Line 326: }
BTW, this won't compile right now if you enable the Kconfig, because in this path, if hob_walker.hob is NULL, then it doesn't have a return path.
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