December 2021 - coreboot-gerrit

Change in coreboot[master]: mb/google/hatch: Remove stryke mainboard
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59875 ) Change subject: mb/google/hatch: Remove stryke mainboard ...................................................................... mb/google/hatch: Remove stryke mainboard The stryke project/mainboard never ended up being and was cancelled early on, therefore remove it from the tree. Change-Id: I4d91fbd4ba0abe0cf599e8e75f04398ef9ff5222 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name D src/mainboard/google/hatch/variants/stryke/Makefile.inc D src/mainboard/google/hatch/variants/stryke/gpio.c D src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl D src/mainboard/google/hatch/variants/stryke/include/variant/ec.h D src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h D src/mainboard/google/hatch/variants/stryke/overridetree.cb 8 files changed, 0 insertions(+), 360 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/59875/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index de68d85..f17882e 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -127,7 +127,6 @@ default "Palkia" if BOARD_GOOGLE_PALKIA default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF - default "Stryke" if BOARD_GOOGLE_STRYKE default "Wyvern" if BOARD_GOOGLE_WYVERN default "Dooly" if BOARD_GOOGLE_DOOLY default "Ambassador" if BOARD_GOOGLE_AMBASSADOR @@ -162,7 +161,6 @@ default "palkia" if BOARD_GOOGLE_PALKIA default "nightfury" if BOARD_GOOGLE_NIGHTFURY default "puff" if BOARD_GOOGLE_PUFF - default "stryke" if BOARD_GOOGLE_STRYKE default "wyvern" if BOARD_GOOGLE_WYVERN default "dooly" if BOARD_GOOGLE_DOOLY default "ambassador" if BOARD_GOOGLE_AMBASSADOR diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 59e2b69..fea4068 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -123,10 +123,6 @@ bool "-> Scout" select BOARD_GOOGLE_BASEBOARD_PUFF -config BOARD_GOOGLE_STRYKE - bool "-> Stryke" - select BOARD_GOOGLE_BASEBOARD_HATCH - config BOARD_GOOGLE_WYVERN bool "-> Wyvern (CTL Chromebox CBx2)" select BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/hatch/variants/stryke/Makefile.inc b/src/mainboard/google/hatch/variants/stryke/Makefile.inc deleted file mode 100644 index ba66a9a..0000000 --- a/src/mainboard/google/hatch/variants/stryke/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -SPD_SOURCES = 4G_2400 # 0b000 -SPD_SOURCES += empty_ddr4 # 0b001 -SPD_SOURCES += 8G_2400 # 0b010 -SPD_SOURCES += 8G_2666 # 0b011 -SPD_SOURCES += 16G_2400 # 0b100 -SPD_SOURCES += 16G_2666 # 0b101 -SPD_SOURCES += 8G_3200 # 0b110 - -bootblock-y += gpio.c -ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c deleted file mode 100644 index 2734629..0000000 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A22 : NC */ - PAD_NC(GPP_A22, NONE), - /* A23 : NC */ - PAD_NC(GPP_A23, NONE), - /* B20 : NC */ - PAD_NC(GPP_B20, NONE), - /* B21 : NC */ - PAD_NC(GPP_B21, NONE), - /* B22 : NC */ - PAD_NC(GPP_B22, NONE), - /* C11 : NC */ - PAD_NC(GPP_C11, NONE), - /* C12 : NC */ - PAD_NC(GPP_C12, NONE), - /* C15 : WWAN_DPR_SAR_ODL - * - * TODO: Driver doesn't use this pin as of now. In case driver starts - * using this pin, expose this pin to driver. - */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - /* F1 : NC */ - PAD_NC(GPP_F1, NONE), - /* F3 : MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_F3, NONE, PLTRST), - /* F10 : MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_F10, NONE, PLTRST), - /* F11 : NC */ - PAD_NC(GPP_F11, NONE), - /* F20 : NC */ - PAD_NC(GPP_F20, NONE), - /* F21 : NC */ - PAD_NC(GPP_F21, NONE), - /* F22 : NC */ - PAD_NC(GPP_F22, NONE), - /* H3 : SPKR_PA_EN */ - PAD_CFG_GPO(GPP_H3, 0, DEEP), - /* H19 : MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_H19, NONE, PLTRST), - /* H22 : MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_H22, NONE, PLTRST), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* - * GPIOs configured before ramstage - * Note: the Hatch platform's romstage will configure - * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins - * as inputs before it reads them, so they are not - * needed in this table. - */ -static const struct pad_config early_gpio_table[] = { - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C8 : UART_PCH_RX_DEBUG_TX */ - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), - /* C9 : UART_PCH_TX_DEBUG_RX */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), - /* F2 : MEM_CH_SEL */ - PAD_CFG_GPI(GPP_F2, NONE, PLTRST), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl deleted file mode 100644 index fd3b5cf..0000000 --- a/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h b/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h deleted file mode 100644 index ce6fbfe..0000000 --- a/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <baseboard/ec.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h b/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h deleted file mode 100644 index be96d95..0000000 --- a/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_H19 -#define GPIO_MEM_CONFIG_1 GPP_H22 -#define GPIO_MEM_CONFIG_2 GPP_F10 -#define GPIO_MEM_CONFIG_3 GPP_F3 - -#endif diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb deleted file mode 100644 index aa73ab6..0000000 --- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb +++ /dev/null @@ -1,218 +0,0 @@ -chip soc/intel/cannonlake - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoDisabled, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 - register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" #Front Camera - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| GSPI1 | | - #| I2C0 | Touchpad | - #| I2C1 | Touch screen | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - }, - }" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - device domain 0 on - device pci 02.0 on # Integrated Graphics Device - register "gfx" = "GMA_DEFAULT_PANEL(0)" - end - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-C Port 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.2 on end - end - chip drivers/usb/acpi - # No Type-A Port 1 - device usb 2.3 off end - end - chip drivers/usb/acpi - # Unused - device usb 2.4 off end - end - chip drivers/usb/acpi - # No WWAN - device usb 2.5 off end - end - chip drivers/usb/acpi - register "desc" = ""Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.6 on end - end - chip drivers/usb/acpi - # Unused - device usb 2.7 off end - end - chip drivers/usb/acpi - # Unused - device usb 2.8 off end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-C Port 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - # No Type-A Port 1 - device usb 3.3 off end - end - chip drivers/usb/acpi - # No WWAN - device usb 3.4 off end - end - chip drivers/usb/acpi - # Unused - device usb 3.5 off end - end - end - end - end # USB xHCI - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" - register "wake" = "GPE0_DW0_21" - register "probed" = "1" - device i2c 15 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "reset_delay_ms" = "100" - register "reset_off_delay_ms" = "5" - register "has_power_resource" = "1" - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" - register "stop_off_delay_ms" = "5" - device i2c 49 on end - end - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" - register "generic.enable_delay_ms" = "12" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 5d on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1e.3 off end # GSPI #1 - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HDA - end - -end -- To view, visit https://review.coreboot.org/c/coreboot/+/59875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91fbd4ba0abe0cf599e8e75f04398ef9ff5222 Gerrit-Change-Number: 59875 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "util/crossgcc: Update gcc to 11.2"
by Mike Banon (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Nico Huber, Branden Waldner, Idwer Vollering, Arthur Heymans, Jacob Garber, Werner Zeh, Iru Cai, Harshit Sharma. Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59636 ) Change subject: Revert "util/crossgcc: Update gcc to 11.2" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I'd like to warn you about GCC upgrade 8.3.0 --> 11.2 which is giving trouble at least for Lenovo G505S (fam15tn). Didn't have the time to investigate it yet, so I'm just reverting a GCC upgrade with this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/59636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a789f9ccb284ac7cad32b12bbf60ecb82efb44 Gerrit-Change-Number: 59636 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:51:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59826 ) Change subject: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake ...................................................................... soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake Check the Alderlake CPU ID to determine if cse sub-paritition update is required or not. BUG=b:202143532 Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59826 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index d33d21f..b9d08c8 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -15,6 +15,7 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <soc/soc_chip.h> +#include <cpu/intel/cpu_ids.h> #include <string.h> #define FSP_SMBIOS_MEMORY_INFO_GUID \ @@ -23,6 +24,11 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } +bool skip_cse_sub_part_update(void) +{ + return cpu_get_cpuid() != CPUID_ALDERLAKE_A2; +} + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Gerrit-Change-Number: 59826 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59685 ) Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update ...................................................................... soc/intel/common: Add support for CSE IOM/NPHY sub-parition update This patch adds the following support to coreboot 1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B partition of BIOS 2. Helper functions to support update. Pre-requisites to enable IOM/NPHY FW Update: 1. NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and FW_MAIN_B through board configuration files. CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path 2. Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition NPHY/IOM update. coreboot follows below procedure to update NPHY and IOM: NPHY Update: 1. coreboot will navigate through the CSE region, identify the CSE’s NPHY FW version and BIOS NPHY version. 2. Compare both versions, if there is a difference, CSE will trigger an NPHY FW update. Otherwise, skips the NPHY FW update. IOM Update: 1. coreboot will navigate through the CSE region, identify CSE's IOM FW version and BIOS IOM version. 2. Compares both versions, if there is a difference, coreboot will trigger an IOM FW update.Otherwise, skip IOM FW update. Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only if CSE boots from CSE RO Boot partition. Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then triggers update of NPHY and IOM FW in the CSE Region(RO and RW). coreboot triggers NPHY/IOM update procedure in all ChromeOS boot modes(Normal and Recovery). BUG=b:202143532 BRANCH=None TEST=Build and verify CSE sub-partitions IOM and NPHY are getting updated with CBFS IOM and NPHY blobs. Verified TBT, type-C display, NVMe, SD card, WWAN, Wifi working after the update. Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59685 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h A src/soc/intel/common/block/include/intelblocks/cse_layout.h 5 files changed, 454 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index d1f4d33..420b511 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -86,6 +86,38 @@ just prior to loading the payload. This is a security feature so the CSE will no longer respond to Pre-Boot commands. +config SOC_INTEL_CSE_SUB_PART_UPDATE + bool "Enable the CSE sub-partition update Feature" + default n + depends on SOC_INTEL_CSE_LITE_SKU + help + This config will enable CSE sub-partition firmware update feature and also will be used ensure + all the required configs are provided by mainboard. + +config SOC_INTEL_CSE_IOM_CBFS_NAME + string "CBFS name for CSE sub-partition IOM binary" if SOC_INTEL_CSE_SUB_PART_UPDATE + default "cse_iom" + help + CBFS entry name for Intel CSE sub-partition IOM binary + +config SOC_INTEL_CSE_IOM_CBFS_FILE + string "Intel CBFS path and file name for CSE sub-partition IOM binary" if SOC_INTEL_CSE_SUB_PART_UPDATE + default "" + help + CBFS path and file name for Intel CSE sub-partition IOM binary + +config SOC_INTEL_CSE_NPHY_CBFS_NAME + string "CBFS name for CSE sub-partition NPHY binary" if SOC_INTEL_CSE_SUB_PART_UPDATE + default "cse_nphy" + help + CBFS entry name for Intel CSE sub-partition NPHY binary + +config SOC_INTEL_CSE_NPHY_CBFS_FILE + string "Intel CBFS path and file name for CSE sub-partition NPHY binary" if SOC_INTEL_CSE_SUB_PART_UPDATE + default "" + help + CBFS path and file name for Intel CSE sub-partition NPHY binary + if STITCH_ME_BIN config CSE_COMPONENTS_PATH diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index eac7d90..a0dc780 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -104,5 +104,23 @@ $(CSE_RW_HASH)-file := $(obj)/cse_rw.hash $(CSE_RW_HASH)-name := $(CSE_RW_HASH) $(CSE_RW_HASH)-type := raw +endif +ifeq ($(CONFIG_SOC_INTEL_CSE_SUB_PART_UPDATE),y) + +CSE_IOM_FILE = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE)) +CSE_IOM = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME)) +regions-for-file-$(CSE_IOM) = FW_MAIN_A,FW_MAIN_B,COREBOOT +cbfs-files-y += $(CSE_IOM) +$(CSE_IOM)-file := $(CSE_IOM_FILE) +$(CSE_IOM)-name := $(CSE_IOM) +$(CSE_IOM)-type := raw + +CSE_NPHY_FILE = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE)) +CSE_NPHY = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME)) +regions-for-file-$(CSE_NPHY) = FW_MAIN_A,FW_MAIN_B,COREBOOT +cbfs-files-y += $(CSE_NPHY) +$(CSE_NPHY)-file := $(CSE_NPHY_FILE) +$(CSE_NPHY)-name := $(CSE_NPHY) +$(CSE_NPHY)-type := raw endif diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 051172f..6edbd84 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -5,9 +5,17 @@ #include <commonlib/region.h> #include <fmap.h> #include <intelblocks/cse.h> +#include <intelblocks/cse_layout.h> #include <security/vboot/vboot_common.h> #include <security/vboot/misc.h> #include <soc/intel/common/reset.h> +#include <arch/cpu.h> + +#define BPDT_HEADER_SZ sizeof(struct bpdt_header) +#define BPDT_ENTRY_SZ sizeof(struct bpdt_entry) +#define SUBPART_HEADER_SZ sizeof(struct subpart_hdr) +#define SUBPART_ENTRY_SZ sizeof(struct subpart_entry) +#define SUBPART_MANIFEST_HDR_SZ sizeof(struct subpart_entry_manifest_header) /* Converts bp index to boot partition string */ #define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO") @@ -627,8 +635,8 @@ struct region_device *target_rdev) { if (region_device_sz(target_rdev) < cse_blob_sz) { - printk(BIOS_ERR, "RW update does not fit. CSE RW flash region size: %zx, Update blob size:%zx\n", - region_device_sz(target_rdev), cse_blob_sz); + printk(BIOS_ERR, "RW update does not fit. CSE RW flash region size: %zx," + "Update blob size:%zx\n", region_device_sz(target_rdev), cse_blob_sz); return CSE_LITE_SKU_LAYOUT_MISMATCH_ERROR; } @@ -727,11 +735,248 @@ return cse_trigger_fw_update(cse_bp_info, status, &target_rdev); } +static const char *cse_sub_part_str(enum bpdt_entry_type type) +{ + switch (type) { + case IOM_FW: + return "IOM"; + case NPHY_FW: + return "NPHY"; + default: + return "Unknown"; + } +} + +static bool cse_sub_part_get_target_rdev(struct region_device *target_rdev, + const char *region_name, enum bpdt_entry_type type) +{ + struct bpdt_header bpdt_hdr; + struct region_device cse_rdev; + struct bpdt_entry bpdt_entries[MAX_SUBPARTS]; + uint8_t i; + + if (fmap_locate_area_as_rdev_rw(region_name, &cse_rdev) < 0) { + printk(BIOS_ERR, "cse_lite: Failed to locate %s in the FMAP\n", region_name); + return false; + } + + if ((rdev_readat(&cse_rdev, &bpdt_hdr, 0, BPDT_HEADER_SZ)) != BPDT_HEADER_SZ) { + printk(BIOS_ERR, "cse_lite: Failed to read BPDT header from CSE region\n"); + return false; + } + + if ((rdev_readat(&cse_rdev, bpdt_entries, BPDT_HEADER_SZ, + (bpdt_hdr.descriptor_count * BPDT_ENTRY_SZ))) != + (bpdt_hdr.descriptor_count * BPDT_ENTRY_SZ)) { + printk(BIOS_ERR, "cse_lite: Failed to read BPDT entries from CSE region\n"); + return false; + } + + /* walk through BPDT entries to identify sub-partition's payload offset and size */ + for (i = 0; i < bpdt_hdr.descriptor_count; i++) { + if (bpdt_entries[i].type == type) { + printk(BIOS_INFO, "cse_lite: Sub-partition %s- offset = 0x%x," + "size = 0x%x\n", cse_sub_part_str(type), bpdt_entries[i].offset, + bpdt_entries[i].size); + + if (rdev_chain(target_rdev, &cse_rdev, bpdt_entries[i].offset, + bpdt_entries[i].size)) + return false; + else + return true; + } + } + + printk(BIOS_ERR, "cse_lite: Sub-partition %s is not found\n", cse_sub_part_str(type)); + return false; +} + +static bool cse_get_sub_part_fw_version(enum bpdt_entry_type type, + const struct region_device *rdev, + struct fw_version *fw_ver) +{ + struct subpart_entry subpart_entry; + struct subpart_entry_manifest_header man_hdr; + + if ((rdev_readat(rdev, &subpart_entry, SUBPART_HEADER_SZ, SUBPART_ENTRY_SZ)) + != SUBPART_ENTRY_SZ) { + printk(BIOS_ERR, "cse_lite: Failed to read %s sub partition entry\n", + cse_sub_part_str(type)); + return false; + } + + if ((rdev_readat(rdev, &man_hdr, subpart_entry.offset_bytes, SUBPART_MANIFEST_HDR_SZ)) + != SUBPART_MANIFEST_HDR_SZ) { + printk(BIOS_ERR, "cse_lite: Failed to read %s Sub part entry #0 manifest\n", + cse_sub_part_str(type)); + return false; + } + + fw_ver->major = man_hdr.binary_version.major; + fw_ver->minor = man_hdr.binary_version.minor; + fw_ver->hotfix = man_hdr.binary_version.hotfix; + fw_ver->build = man_hdr.binary_version.build; + + return true; +} + +static void cse_sub_part_get_source_fw_version(void *subpart_cbfs_rw, struct fw_version *fw_ver) +{ + uint8_t *ptr = (uint8_t *)subpart_cbfs_rw; + struct subpart_entry *subpart_entry; + struct subpart_entry_manifest_header *man_hdr; + + subpart_entry = (struct subpart_entry *) (ptr + SUBPART_HEADER_SZ); + man_hdr = (struct subpart_entry_manifest_header *) (ptr + subpart_entry->offset_bytes); + + fw_ver->major = man_hdr->binary_version.major; + fw_ver->minor = man_hdr->binary_version.minor; + fw_ver->hotfix = man_hdr->binary_version.hotfix; + fw_ver->build = man_hdr->binary_version.build; +} + +static bool cse_prep_for_component_update(const struct cse_bp_info *cse_bp_info) +{ + /* + * To set CSE's operation mode to HMRFPO mode: + * 1. Ensure CSE to boot from RO(BP1) + * 2. Send HMRFPO_ENABLE command to CSE + */ + if (!cse_boot_to_ro(cse_bp_info)) + return false; + + return cse_hmrfpo_enable(); +} + +static uint8_t cse_sub_part_trigger_update(enum bpdt_entry_type type, uint8_t bp, + const void *subpart_cbfs_rw, const size_t blob_sz, + struct region_device *target_rdev) +{ + if (region_device_sz(target_rdev) < blob_sz) { + printk(BIOS_ERR, "cse_lite: %s Target sub-partition size: %zx, " + "smaller than blob size:%zx, abort update\n", + cse_sub_part_str(type), region_device_sz(target_rdev), blob_sz); + return CSE_LITE_SKU_SUB_PART_LAYOUT_MISMATCH_ERROR; + } + + /* Erase CSE Lite sub-partition */ + if (!cse_erase_rw_region(target_rdev)) + return CSE_LITE_SKU_SUB_PART_UPDATE_FAIL; + + /* Update CSE Lite sub-partition */ + if (!cse_copy_rw(target_rdev, (void *)subpart_cbfs_rw, 0, blob_sz)) + return CSE_LITE_SKU_SUB_PART_UPDATE_FAIL; + + printk(BIOS_INFO, "cse_lite: CSE %s %s Update successful\n", GET_BP_STR(bp), + cse_sub_part_str(type)); + + return CSE_LITE_SKU_PART_UPDATE_SUCCESS; +} + +static uint8_t handle_cse_sub_part_fw_update_rv(uint8_t rv) +{ + switch (rv) { + case CSE_LITE_SKU_PART_UPDATE_SUCCESS: + case CSE_LITE_SKU_SUB_PART_UPDATE_NOT_REQ: + return rv; + default: + cse_trigger_vboot_recovery(rv); + } + /* Control never reaches here */ + return rv; +} + +static enum csme_failure_reason cse_sub_part_fw_component_update(enum bpdt_entry_type type, + const struct cse_bp_info *cse_bp_info, const char *name) +{ + struct region_device target_rdev; + struct fw_version target_fw_ver, source_fw_ver; + enum csme_failure_reason rv; + size_t size; + static const char * const cse_regions[] = {"CSE_RO", "CSE_RW"}; + + void *subpart_cbfs_rw = cbfs_map(name, &size); + if (!subpart_cbfs_rw) { + printk(BIOS_ERR, "cse_lite: Not able to map %s CBFS file\n", + cse_sub_part_str(type)); + return CSE_LITE_SKU_SUB_PART_BLOB_ACCESS_ERR; + } + + cse_sub_part_get_source_fw_version(subpart_cbfs_rw, &source_fw_ver); + printk(BIOS_INFO, "cse_lite: CBFS %s FW Version: %x.%x.%x.%x\n", cse_sub_part_str(type), + source_fw_ver.major, source_fw_ver.minor, source_fw_ver.hotfix, + source_fw_ver.build); + + /* Trigger sub-partition update in CSE RO and CSE RW */ + for (size_t bp = 0; bp < ARRAY_SIZE(cse_regions); bp++) { + if (!cse_sub_part_get_target_rdev(&target_rdev, cse_regions[bp], type)) { + rv = CSE_LITE_SKU_SUB_PART_ACCESS_ERR; + goto error_exit; + } + + if (!cse_get_sub_part_fw_version(type, &target_rdev, &target_fw_ver)) { + rv = CSE_LITE_SKU_SUB_PART_ACCESS_ERR; + goto error_exit; + } + + printk(BIOS_INFO, "cse_lite: %s %s FW Version: %x.%x.%x.%x\n", cse_regions[bp], + cse_sub_part_str(type), target_fw_ver.major, + target_fw_ver.minor, target_fw_ver.hotfix, target_fw_ver.build); + + if (!cse_compare_sub_part_version(&target_fw_ver, &source_fw_ver)) { + printk(BIOS_INFO, "cse_lite: %s %s update is not required\n", + cse_regions[bp], cse_sub_part_str(type)); + rv = CSE_LITE_SKU_SUB_PART_UPDATE_NOT_REQ; + continue; + } + + printk(BIOS_INFO, "CSE %s %s Update initiated\n", GET_BP_STR(bp), + cse_sub_part_str(type)); + + if (!cse_prep_for_component_update(cse_bp_info)) { + rv = CSE_LITE_SKU_SUB_PART_ACCESS_ERR; + goto error_exit; + } + + rv = cse_sub_part_trigger_update(type, bp, subpart_cbfs_rw, + size, &target_rdev); + + if (rv != CSE_LITE_SKU_PART_UPDATE_SUCCESS) + goto error_exit; + } +error_exit: + cbfs_unmap(subpart_cbfs_rw); + return rv; +} + +static uint8_t cse_sub_part_fw_update(const struct cse_bp_info *cse_bp_info) +{ + if (skip_cse_sub_part_update()) { + printk(BIOS_INFO, "CSE Sub-partition update not required\n"); + return CSE_LITE_SKU_SUB_PART_UPDATE_NOT_REQ; + } + + int rv; + rv = cse_sub_part_fw_component_update(IOM_FW, cse_bp_info, + CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME); + + handle_cse_sub_part_fw_update_rv(rv); + + rv = cse_sub_part_fw_component_update(NPHY_FW, cse_bp_info, + CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME); + + return handle_cse_sub_part_fw_update_rv(rv); +} + void cse_fw_sync(void) { static struct get_bp_info_rsp cse_bp_info; - if (vboot_recovery_mode_enabled()) { + /* + * If system is in recovery mode, skip CSE Lite update if CSE sub-partition update + * is not enabled and continue to update CSE sub-partitions. + */ + if (vboot_recovery_mode_enabled() && !CONFIG(SOC_INTEL_CSE_SUB_PART_UPDATE)) { printk(BIOS_DEBUG, "cse_lite: Skip switching to RW in the recovery path\n"); return; } @@ -744,7 +989,31 @@ if (!cse_get_bp_info(&cse_bp_info)) { printk(BIOS_ERR, "cse_lite: Failed to get CSE boot partition info\n"); - cse_trigger_vboot_recovery(CSE_COMMUNICATION_ERROR); + + /* If system is in recovery mode, don't trigger recovery again */ + if (!vboot_recovery_mode_enabled()) { + cse_trigger_vboot_recovery(CSE_COMMUNICATION_ERROR); + } else { + printk(BIOS_ERR, "cse_lite: System is already in Recovery Mode, " + "so no action\n"); + return; + } + } + + /* + * If system is in recovery mode, CSE Lite update has to be skipped but CSE + * sub-partitions like NPHY and IOM have to to be updated. If CSE sub-parition update + * fails during recovery, just continue to boot. + */ + if (CONFIG(SOC_INTEL_CSE_SUB_PART_UPDATE) && vboot_recovery_mode_enabled()) { + if (cse_sub_part_fw_update(&cse_bp_info.bp_info) == + CSE_LITE_SKU_PART_UPDATE_SUCCESS) { + cse_board_reset(); + do_global_reset(); + die("ERROR: GLOBAL RESET Failed to reset the system\n"); + } + + return; } if (!cse_fix_data_failure_err(&cse_bp_info.bp_info)) @@ -761,6 +1030,9 @@ cse_trigger_vboot_recovery(rv); } + if (CONFIG(SOC_INTEL_CSE_SUB_PART_UPDATE)) + cse_sub_part_fw_update(&cse_bp_info.bp_info); + if (!cse_is_rw_bp_status_valid(&cse_bp_info.bp_info)) cse_trigger_vboot_recovery(CSE_LITE_SKU_RW_JUMP_ERROR); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 4184b17..68f1d3c 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -143,6 +143,24 @@ /* Error sending EOP to CSE */ CSE_EOP_FAIL = 12, + + /* CSE Sub-partition update fail */ + CSE_LITE_SKU_SUB_PART_UPDATE_FAIL = 13, + + /* CSE sub-partition access failure */ + CSE_LITE_SKU_SUB_PART_ACCESS_ERR = 14, + + /* CSE CBFS sub-partition access error */ + CSE_LITE_SKU_SUB_PART_BLOB_ACCESS_ERR = 15, + + /* CSE Lite sub-partition update is not required */ + CSE_LITE_SKU_SUB_PART_UPDATE_NOT_REQ = 16, + + /* CSE Lite sub-partition layout mismatch error */ + CSE_LITE_SKU_SUB_PART_LAYOUT_MISMATCH_ERROR = 17, + + /* CSE Lite sub-partition update success */ + CSE_LITE_SKU_PART_UPDATE_SUCCESS = 18, }; /* set up device for use in early boot enviroument with temp bar */ @@ -320,4 +338,9 @@ /* Function that put the CSE into desired state based on `requested_state` */ bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state); +/* + * Check if cse sub-parition update is required or not. + * Returns true if cse sub-parition update is required otherwise false. + */ +bool skip_cse_sub_part_update(void); #endif // SOC_INTEL_COMMON_CSE_H diff --git a/src/soc/intel/common/block/include/intelblocks/cse_layout.h b/src/soc/intel/common/block/include/intelblocks/cse_layout.h new file mode 100644 index 0000000..4c88cc5 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_layout.h @@ -0,0 +1,105 @@ +/* BPDT version 1.7 support */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <sys/types.h> + +enum bpdt_entry_type { + SMIP = 0, + CSE_RBE = 1, + CSE_BUP = 2, + UCODE = 3, + IBB = 4, + S_BPDT = 5, + OBB = 6, + CSE_MAIN = 7, + ISH = 8, + CSE_IDLM = 9, + IFP_OVERRIDE = 10, + UTOK = 11, + UFS_PHY = 12, + UFS_GPP = 13, + PMC = 14, + IUNIT = 15, + NVM_CFG = 16, + UEP = 17, + OEM_KM = 20, + PAVP = 22, + IOM_FW = 23, + NPHY_FW = 24, + TBT_FW = 25, + ICC = 32, + + MAX_SUBPARTS, +}; + +struct bpdt_header { + uint32_t signature; /* BPDT_SIGNATURE */ + uint16_t descriptor_count; + uint8_t version; /* Layout 1.7 = 2 */ + uint8_t flags; + uint32_t checksum; + uint32_t ifwi_version; + struct { + uint16_t major; + uint16_t minor; + uint16_t build; + uint16_t hotfix; + } fit_tool_version; +} __packed; + +struct cse_layout { + uint8_t rom_bypass[16]; + uint16_t size; + uint16_t redundancy; + uint32_t checksum; + uint32_t data_offset; + uint32_t data_size; + uint32_t bp1_offset; + uint32_t bp1_size; + uint32_t bp2_offset; + uint32_t bp2_size; + uint32_t bp3_offset; + uint32_t bp3_size; + uint32_t bp4_offset; + uint32_t bp4_size; + uint32_t bp5_offset; + uint32_t bp5_size; + uint32_t temp_base_addr; + uint32_t temp_base_size; + uint32_t flog_offset; + uint32_t flog_size; +} __packed; + +struct bpdt_entry { + uint32_t type; + uint32_t offset; + uint32_t size; +} __packed; + +struct subpart_hdr { + uint32_t signature; /* SUBPART_SIGNATURE */ + uint32_t count; + uint8_t hdr_version; /* Header version = 2 */ + uint8_t entry_version; /* Entry version = 1 */ + uint8_t length; + uint8_t reserved; + uint8_t name[4]; + uint32_t checksum; +} __packed; + +struct subpart_entry { + uint8_t name[12]; + uint32_t offset_bytes; + uint32_t length; + uint32_t rsvd2; +} __packed; + +struct subpart_entry_manifest_header { + uint8_t reserved[36]; + struct { + uint16_t major; + uint16_t minor; + uint16_t build; + uint16_t hotfix; + } binary_version; +} __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 19 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Julius Werner, Krishna P Bhat D. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59685 ) Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update ...................................................................... Patch Set 18: (1 comment) Patchset: PS18: Thanks Krishna! -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 18 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:47:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add check before sending HMRFPO_ENABLE command
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59698 ) Change subject: soc/intel/common: Add check before sending HMRFPO_ENABLE command ...................................................................... soc/intel/common: Add check before sending HMRFPO_ENABLE command This patch adds a check to determine if the CSE's current operation mode is ME_HFS1_COM_SECOVER_MEI_MSG or not before sending HMRFPO_ENABLE command to CSE. If CSE is already in the ME_HFS1_COM_SECOVER_MEI_MSG, coreboot skips sending HMRFPO_ENABLE command to CSE to unlock the CSE RW partition. TEST=Verify sending HMRFPO_ENABLE command on Brya system. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59698 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index b46d3e4..a80ab48 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -744,6 +744,12 @@ struct hmrfpo_enable_resp resp; size_t resp_size = sizeof(struct hmrfpo_enable_resp); + if (cse_is_hfs1_com_secover_mei_msg()) { + printk(BIOS_DEBUG, "HECI: CSE is already in security override mode, " + "skip sending HMRFPO_ENABLE command to CSE\n"); + return 1; + } + printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n"); if (!cse_is_hmrfpo_enable_allowed()) { -- To view, visit https://review.coreboot.org/c/coreboot/+/59698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b Gerrit-Change-Number: 59698 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Rename compare_cse_version() function name
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59689 ) Change subject: soc/intel/common: Rename compare_cse_version() function name ...................................................................... soc/intel/common: Rename compare_cse_version() function name The patch renames the compare_cse_version() function to the cse_compare_sub_part_version(). It makes the function generic so that it can be used to compare version of any CSE sub-partition like IOM, NPHY etc. TEST=Verified build for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I88a44a3c0ba2ad8a589602a35ea644dab535b287 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59689 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Krishna P Bhat D: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index bb64444..051172f 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -476,12 +476,13 @@ } /* - * Compare versions of CSE CBFS RW and CSE RW partition + * Compare versions of CSE CBFS sub-component and CSE sub-component partition + * In case of CSE component comparison: * If ver_cmp_status = 0, no update is required * If ver_cmp_status < 0, coreboot downgrades CSE RW region * If ver_cmp_status > 0, coreboot upgrades CSE RW region */ -static int compare_cse_version(const struct fw_version *a, const struct fw_version *b) +static int cse_compare_sub_part_version(const struct fw_version *a, const struct fw_version *b) { if (a->major != b->major) return a->major - b->major; @@ -590,7 +591,7 @@ cbfs_unmap(version_str); - ret = compare_cse_version(&cbfs_rw_version, cse_get_rw_version(cse_bp_info)); + ret = cse_compare_sub_part_version(&cbfs_rw_version, cse_get_rw_version(cse_bp_info)); if (ret == 0) return CSE_UPDATE_NOT_REQUIRED; else if (ret < 0) 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88a44a3c0ba2ad8a589602a35ea644dab535b287 Gerrit-Change-Number: 59689 Gerrit-PatchSet: 10 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: driver/i2c: Add sx9360 driver
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Gwendal Grignou. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59608 ) Change subject: driver/i2c: Add sx9360 driver ...................................................................... Patch Set 2: (1 comment) File src/drivers/i2c/sx9360/sx9360.c: https://review.coreboot.org/c/coreboot/+/59608/comment/c890dcc3_acffe928 PS2, Line 15: REGISTER This looks unused, and not particularly worth it for 3 parameters? If it becomes a bigger list, you can do the same thing with an array of structs instead of the preprocessor -- To view, visit https://review.coreboot.org/c/coreboot/+/59608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a912f184e6f3501f894cca24c0d71a2c3087516 Gerrit-Change-Number: 59608 Gerrit-PatchSet: 2 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:46:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for x86_64 [Don't merge]
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59745 ) Change subject: soc/intel/alderlake: Add support for x86_64 [Don't merge] ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/59745/comment/edac2f01_981ee6c3 PS5, Line 46: PLATFORM_USES_FSP2_X86_64 you gotta let me know how to try this out 😄 -- To view, visit https://review.coreboot.org/c/coreboot/+/59745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ea8fd9986224b0b552e982ecc2cbef07bdcca78 Gerrit-Change-Number: 59745 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:42:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64)
by Tim Wawrzynczak (Code Review) Dec. 3, 2021

Dec. 3, 2021

Attention is currently required from: Subrata Banik, Wonkyu Kim, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Tim Chu, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59744 ) Change subject: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64) ...................................................................... Patch Set 7: (2 comments) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/59744/comment/50354ec7_59b60d97 PS6, Line 41: uint64_t > > it looks only address related parameters are changed to 64bit. […] I agree with Arthur here, explicit is better with ABIs. File src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/59744/comment/a3c416fc_698a818a PS7, Line 192: Note: This ought to be VOID*, but that won't allow calling this binary on x86_64. > not up to date anymore ;-) 🎉 -- To view, visit https://review.coreboot.org/c/coreboot/+/59744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If12b63a282c660da6f57fe23b0b848e2d155853f Gerrit-Change-Number: 59744 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Dec 2021 21:41:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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