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David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59677 )
Change subject: Documentation: Add template for deprecation notices
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
File Documentation/releases/templates.md:
https://review.coreboot.org/c/coreboot/+/59677/comment/9250413c_2d06dcdc
PS4, Line 25: line out
outline
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Change subject: mb/google/brya/var/vell: update gpio override
......................................................................
Patch Set 15:
(1 comment)
File src/mainboard/google/brya/variants/vell/gpio.c:
https://review.coreboot.org/c/coreboot/+/59305/comment/433b9545_aae055c9
PS14, Line 115: PAD_CFG_GPO(GPP_D2, 1, DEEP),
> For proper power sequencing of the SSD, you will likely need to enable power for SSD here as well, i […]
Done
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Shon Wang has uploaded a new patch set (#15) to the change originally created by Kevin Chiu. ( https://review.coreboot.org/c/coreboot/+/59305 )
Change subject: mb/google/brya/var/vell: update gpio override
......................................................................
mb/google/brya/var/vell: update gpio override
Configure GPIOs according to schematics
Update initial gpio configuration for redrix
BUG=b:205908918
TEST=emerge-brya coreboot
Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0
Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
---
A src/mainboard/google/brya/variants/vell/Makefile.inc
A src/mainboard/google/brya/variants/vell/gpio.c
2 files changed, 188 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/59305/15
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9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59642 )
Change subject: mb/google/dedede/var/drawcia: Generate new SPD ID for new memory parts
......................................................................
Patch Set 6:
Automatic boot test returned (PASS/FAIL/TOTAL): 5 / 4 / 9
FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500
and payload SeaBIOS : https://lava.9esec.io/r/83345
FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64
and payload SeaBIOS : https://lava.9esec.io/r/83343
FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC
and payload SeaBIOS : https://lava.9esec.io/r/83342
FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG
and payload SeaBIOS : https://lava.9esec.io/r/83341
PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35
and payload SeaBIOS : https://lava.9esec.io/r/83340
PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64
and payload SeaBIOS : https://lava.9esec.io/r/83339
PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN
and payload SeaBIOS : https://lava.9esec.io/r/83338
PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_
and payload SeaBIOS : https://lava.9esec.io/r/83337
PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX
and payload SeaBIOS : https://lava.9esec.io/r/83336
Please note: This test is under development and might not be accurate at all!
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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59861 )
Change subject: mb/google/brya/var/felwinter: Correct garage wake event
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59861/comment/df1aee95_e7cfa015
PS1, Line 9: Eject event is high. Set wake event to active high.
> suggestion, add something like: […]
Done
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59861
to look at the new patch set (#2).
Change subject: mb/google/brya/var/felwinter: Correct garage wake event
......................................................................
mb/google/brya/var/felwinter: Correct garage wake event
Eject event is high. Set wake event to active high. The polarity of the SCI and the wakeup_event_action for the pen ejection feature were both
backwards, and was causing the system to fail to enter sleep states
because the event was always asserted.
BUG=b:208937710
TEST=only release switch can wake system.
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: I568e9175c7a66599f7a525c32e4def7a79b55a0a
---
M src/mainboard/google/brya/variants/felwinter/gpio.c
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/59861/2
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9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59491 )
Change subject: libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser
......................................................................
Patch Set 6:
Automatic boot test returned (PASS/FAIL/TOTAL): 4 / 4 / 8
FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500
and payload SeaBIOS : https://lava.9esec.io/r/83334
FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64
and payload SeaBIOS : https://lava.9esec.io/r/83332
FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC
and payload SeaBIOS : https://lava.9esec.io/r/83331
FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG
and payload SeaBIOS : https://lava.9esec.io/r/83330
PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64
and payload SeaBIOS : https://lava.9esec.io/r/83328
PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN
and payload SeaBIOS : https://lava.9esec.io/r/83327
PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_
and payload SeaBIOS : https://lava.9esec.io/r/83326
PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX
and payload SeaBIOS : https://lava.9esec.io/r/83325
Please note: This test is under development and might not be accurate at all!
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Attention is currently required from: Raul Rangel, Patrick Georgi, Tim Wawrzynczak.
Hello Raul Rangel, Patrick Georgi, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59877
to look at the new patch set (#2).
Change subject: cbfstool: Fix offset calculation for aligned files
......................................................................
cbfstool: Fix offset calculation for aligned files
The placement calculation logic in cbfs_add_component() has become quite
a mess, and this patch can only fix that to a limited degree. The
interaction between all the different pathways of how the `offset`
variable can be set and at what point exactly the final placement offset
is decided can get quite convoluted. In particular, one existing problem
is that the offset for a file added with the --align flag is decided
before the convert() function is called, which may change the form (and
thereby the size) of the file again after its location was found --
resulting in a location that ends up being too small, or being unable to
find a location for a file that should fit. This used to be okay under
the assumption that forced alignment should really only be necessary for
use cases like XIP where the file is directly "used" straight from its
location on flash in some way, and those cases can never be compressed
-- however, recent AMD platforms have started using the --align flag to
meet the requirements of their SPI DMA controller and broken this
assumption.
This patch fixes that particular problem and hopefully eliminates a bit
of the convolution by moving the offset decision point in the --align
case after the convert() step. This is safe when the steps in-between
(add_topswap_bootblock() and convert() itself) do not rely on the
location having already been decided by --align before that point. For
the topswap case this is easy, because in practice we always call it
with --base-address (and as far as I can tell that's the only way it was
ever meant to work?) -- so codify that assumption in the function. For
convert() this mostly means that the implementations that do touch the
offset variable (mkstage and FSP) need to ensure they take care of the
alignment themselves. The FSP case is particularly complex so I tried to
rewrite the code in a slightly more straight-forward way and clearly
document the supported cases, which should hopefully make it easier to
see that the offset variable is handled correctly in all of them. For
mkstage the best solution seems to be to only have it touch the offset
variable in the XIP case (where we know compression must be disabled, so
we can rely on it not changing the file size later), and have the extra
space for the stage header directly taken care of by do_cbfs_locate() so
that can happen after convert().
NOTE: This is changing the behavior of `cbfstool add -t fsp` when
neither --base-address nor --xip are passed (e.g. FSP-S). Previously,
cbfstool would implicitly force an alignment of 4K. As far as I can tell
from the comments, this is unnecessary because this binary is loaded
into RAM and CBFS placement does not matter, so I assume this is an
oversight caused by accidentally reusing code that was only meant for
the XIP case.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: Ia49a585988f7a74944a6630b77b3ebd79b3a9897
---
M util/cbfstool/cbfstool.c
1 file changed, 82 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/59877/2
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