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Change subject: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59826/comment/840fe8dd_0594029e
PS4, Line 11:
`BUG=b:202143532`
as well
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Change subject: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
......................................................................
Patch Set 18: Code-Review+2
(2 comments)
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/59685/comment/d636c43a_fb10d205
PS16, Line 405:
: __weak bool skip_cse_sub_part_update(void)
: {
: return false;
: }
> Done
Well, honestly I have no idea if we'll come across this case again, but I wouldn't be surprised.
https://review.coreboot.org/c/coreboot/+/59685/comment/a7e0ad77_eaec29a2
PS16, Line 805:
> When fmap_locate_area_as_rdev_rw() is used to get the target region device, there is no mmap/munmap […]
Oh that's true, you only get mmap on the ro device.
I guess you could refactor this so they can still share the fw_ver->{major,minor...} lines, but that seems not particularly worth it here.
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Change subject: mb/google/guybrush: Separate signed amdfw
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
Hopefully once CBFS_VERIFICATION is ready we won't need to do this.
File src/mainboard/google/guybrush/Kconfig:
https://review.coreboot.org/c/coreboot/+/59867/comment/3d0dd5d2_a9edc84e
PS2, Line 59: y
We don't want to enable this until we are passing the hash table to the PSP and it is verifying it.
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Change subject: arch/x86/id.S: Fix building with clang
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51500/comment/6654c0b2_01809197
PS1, Line 7: arch/x86/id.S: Fix building with clang
> Can you quote the error message this fixes?
```
CC bootblock/arch/x86/id.o
/tmp/id-35b17a.s:35:7: error: expected relocatable expression
.long - ver
^
/tmp/id-35b17a.s:36:7: error: expected relocatable expression
.long - vendor
^
/tmp/id-35b17a.s:37:7: error: expected relocatable expression
.long - part
^
```
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Change subject: mb/acer/g43t-am3: Add documentation
......................................................................
Patch Set 2:
(1 comment)
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PS2:
Can this be submitted?
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Change subject: soc/intel/common: Add check before sending HMRFPO_ENABLE command
......................................................................
Patch Set 8: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59642 )
Change subject: mb/google/dedede/var/drawcia: Generate new SPD ID for new memory parts
......................................................................
mb/google/dedede/var/drawcia: Generate new SPD ID for new memory parts
Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Samsung K4U6E3S4AA-MGCL
BUG=b:204014463
TEST=run part_id_gen to generate SPD id
Change-Id: Icb0f211508450b16b2e5d214ae6adc9852718a59
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59642
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc
M src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
3 files changed, 3 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc
index 96284d1..f975bfb 100644
--- a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc
@@ -4,4 +4,4 @@
# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/drawcia/memory src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
SPD_SOURCES =
-SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL
+SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL, K4U6E3S4AA-MGCL
diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt
index 78cc95d..8a3c5c8 100644
--- a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt
@@ -10,3 +10,4 @@
MT53E512M32D1NP-046 WT:B 0 (0000)
H54G46CYRBX267 0 (0000)
K4U6E3S4AB-MGCL 0 (0000)
+K4U6E3S4AA-MGCL 0 (0000)
diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
index f195c25..4a3e217 100644
--- a/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
@@ -4,3 +4,4 @@
MT53E512M32D1NP-046 WT:B
H54G46CYRBX267
K4U6E3S4AB-MGCL
+K4U6E3S4AA-MGCL
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