coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Krishna P Bhat D, Nick Vaccaro, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59826 ) Change subject: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59826/comment/840fe8dd_0594029e PS4, Line 11: `BUG=b:202143532` as well -- To view, visit https://review.coreboot.org/c/coreboot/+/59826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Gerrit-Change-Number: 59826 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 17:38:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Krishna P Bhat D, Nick Vaccaro, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59826 ) Change subject: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Gerrit-Change-Number: 59826 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 17:37:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Julius Werner, Krishna P Bhat D. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59685 ) Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update ...................................................................... Patch Set 18: Code-Review+2 (2 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/59685/comment/d636c43a_fb10d205 PS16, Line 405: : __weak bool skip_cse_sub_part_update(void) : { : return false; : } > Done Well, honestly I have no idea if we'll come across this case again, but I wouldn't be surprised. https://review.coreboot.org/c/coreboot/+/59685/comment/a7e0ad77_eaec29a2 PS16, Line 805: > When fmap_locate_area_as_rdev_rw() is used to get the target region device, there is no mmap/munmap […] Oh that's true, you only get mmap on the ro device. I guess you could refactor this so they can still share the fw_ver->{major,minor...} lines, but that seems not particularly worth it here. -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 18 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 17:36:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Separate signed amdfw
by Raul Rangel (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59867 ) Change subject: mb/google/guybrush: Separate signed amdfw ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: Hopefully once CBFS_VERIFICATION is ready we won't need to do this. File src/mainboard/google/guybrush/Kconfig: https://review.coreboot.org/c/coreboot/+/59867/comment/3d0dd5d2_a9edc84e PS2, Line 59: y We don't want to enable this until we are passing the hash table to the PSP and it is verifying it. -- To view, visit https://review.coreboot.org/c/coreboot/+/59867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4fd3cff11a38d82afb8c5ce379f1d1b5b9adfbf Gerrit-Change-Number: 59867 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Dec 2021 17:16:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/id.S: Fix building with clang
by Paul Menzel (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51500 ) Change subject: arch/x86/id.S: Fix building with clang ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51500/comment/6654c0b2_01809197 PS1, Line 7: arch/x86/id.S: Fix building with clang > Can you quote the error message this fixes? ``` CC bootblock/arch/x86/id.o /tmp/id-35b17a.s:35:7: error: expected relocatable expression .long - ver ^ /tmp/id-35b17a.s:36:7: error: expected relocatable expression .long - vendor ^ /tmp/id-35b17a.s:37:7: error: expected relocatable expression .long - part ^ ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/51500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I930e7b96c4428bcb95ff1903e6a3e7679171ffee Gerrit-Change-Number: 51500 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 17:12:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/acer/g43t-am3: Add documentation
by Paul Menzel (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Felix Singer, Angel Pons, Michael Büchler. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56838 ) Change subject: mb/acer/g43t-am3: Add documentation ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Can this be submitted? -- To view, visit https://review.coreboot.org/c/coreboot/+/56838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e296b3efbff0260f32badc699f1062f9885fa53 Gerrit-Change-Number: 56838 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Comment-Date: Fri, 03 Dec 2021 16:55:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add check before sending HMRFPO_ENABLE command
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Krishna P Bhat D, Kane Chen, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59698 ) Change subject: soc/intel/common: Add check before sending HMRFPO_ENABLE command ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b Gerrit-Change-Number: 59698 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 16:53:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: Swap TPM I2C with touchscreen I2C
by Tim Wawrzynczak (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Chen Wisley, Wisley Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59863 ) Change subject: mb/google/brya/var/redrix: Swap TPM I2C with touchscreen I2C ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a8339c23522019da884944246427512170510b6 Gerrit-Change-Number: 59863 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 16:51:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser
by Felix Held (Code Review) 03 Dec '21

03 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59491 ) Change subject: libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser ...................................................................... libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser coreboot stores much information in the CBMEM IMD. Until now it was ignored. This patch makes use of these coreboot tables entries. It also removes get_cbmem_addr() function as it is no longer needed. Moreover, the coreboot tables entry CB_TAG_MRC_CACHE does not exist anymore, as it is not created by the code. It was replaced by CBMEM_ID_MRCDATA entry, so MRCDATA should now be accessible through sysinfo structure field. Change-Id: I5bd02a98ba2631f34014bc0f8e7ebd5a5ddd2321 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59491 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M payloads/libpayload/arch/x86/coreboot.c M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c 4 files changed, 71 insertions(+), 88 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index 38ede87..cad1396 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -47,20 +47,12 @@ info->x86_rom_var_mtrr_index = rom_mtrr->index; } -static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info) -{ - info->mrc_cache = get_cbmem_addr(ptr); -} - int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) { switch(rec->tag) { case CB_TAG_X86_ROM_MTRR: cb_parse_x86_rom_var_mtrr(rec, info); break; - case CB_TAG_MRC_CACHE: - cb_parse_mrc_cache(rec, info); - break; default: return 0; } diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 914cfa5..3fd3fc8 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -321,6 +321,16 @@ uint64_t boot_media_size; }; + +struct cb_cbmem_entry { + uint32_t tag; + uint32_t size; + + uint64_t address; + uint32_t entry_size; + uint32_t id; +}; + struct cb_tsc_info { uint32_t tag; uint32_t size; @@ -443,6 +453,4 @@ (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ + (sizeof((_rec)->map[0]) * (_idx))) -/* Helper functions */ -uintptr_t get_cbmem_addr(const void *cbmem_tab_entry); #endif diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index b34476d..376f298 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -150,6 +150,12 @@ #endif /* USB Type-C Port Configuration Info */ uintptr_t type_c_info; + + /* CBFS RW/RO Metadata Cache */ + uintptr_t cbfs_ro_mcache_offset; + uint32_t cbfs_ro_mcache_size; + uintptr_t cbfs_rw_mcache_offset; + uint32_t cbfs_rw_mcache_size; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index bd10411..79a382b 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -29,6 +29,7 @@ #include <libpayload-config.h> #include <libpayload.h> +#include <commonlib/bsd/cbmem_id.h> #include <coreboot_tables.h> #include <stdint.h> @@ -41,12 +42,6 @@ /* === Parsing code === */ /* This is the generic parsing code. */ -uintptr_t get_cbmem_addr(const void *const cbmem_tab_entry) -{ - const struct cb_cbmem_tab *const cbmem = cbmem_tab_entry; - return cbmem->cbmem_tab; -} - static void cb_parse_memory(void *ptr, struct sysinfo_t *info) { struct cb_memory *mem = ptr; @@ -83,11 +78,6 @@ info->cb_serial = virt_to_phys(ptr); } -static void cb_parse_vboot_workbuf(unsigned char *ptr, struct sysinfo_t *info) -{ - info->vboot_workbuf = get_cbmem_addr(ptr); -} - static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) { struct lb_range *vbnv = (struct lb_range *)ptr; @@ -128,26 +118,6 @@ info->macs[i] = macs->mac_addrs[i]; } -static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) -{ - info->tstamp_table = get_cbmem_addr(ptr); -} - -static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) -{ - info->cbmem_cons = get_cbmem_addr(ptr); -} - -static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) -{ - info->acpi_gnvs = get_cbmem_addr(ptr); -} - -static void cb_parse_acpi_cnvs(unsigned char *ptr, struct sysinfo_t *info) -{ - info->acpi_cnvs = get_cbmem_addr(ptr); -} - static void cb_parse_board_config(unsigned char *ptr, struct sysinfo_t *info) { struct cb_board_config *const config = (struct cb_board_config *)ptr; @@ -188,11 +158,6 @@ *info = virt_to_phys(str->string); } -static void cb_parse_wifi_calibration(void *ptr, struct sysinfo_t *info) -{ - info->wifi_calibration = get_cbmem_addr(ptr); -} - static void cb_parse_ramoops(void *ptr, struct sysinfo_t *info) { struct lb_range *ramoops = (struct lb_range *)ptr; @@ -236,21 +201,6 @@ info->boot_media_size = bmp->boot_media_size; } -static void cb_parse_vpd(void *ptr, struct sysinfo_t *info) -{ - info->chromeos_vpd = get_cbmem_addr(ptr); -} - -static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info) -{ - info->fmap_cache = get_cbmem_addr(ptr); -} - -static void cb_parse_type_c_info(void *ptr, struct sysinfo_t *info) -{ - info->type_c_info = get_cbmem_addr(ptr); -} - #if CONFIG(LP_TIMER_RDTSC) static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info) { @@ -264,6 +214,57 @@ } #endif +static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info) +{ + const struct cb_cbmem_entry *cbmem_entry = ptr; + + if (cbmem_entry->size != sizeof(*cbmem_entry)) + return; + + switch (cbmem_entry->id) { + case CBMEM_ID_ACPI_CNVS: + info->acpi_cnvs = cbmem_entry->address; + break; + case CBMEM_ID_ACPI_GNVS: + info->acpi_gnvs = cbmem_entry->address; + break; + case CBMEM_ID_CBFS_RO_MCACHE: + info->cbfs_ro_mcache_offset = cbmem_entry->address; + info->cbfs_ro_mcache_size = cbmem_entry->size; + break; + case CBMEM_ID_CBFS_RW_MCACHE: + info->cbfs_rw_mcache_offset = cbmem_entry->address; + info->cbfs_rw_mcache_size = cbmem_entry->size; + break; + case CBMEM_ID_CONSOLE: + info->cbmem_cons = cbmem_entry->address; + break; + case CBMEM_ID_MRCDATA: + info->mrc_cache = cbmem_entry->address; + break; + case CBMEM_ID_VBOOT_WORKBUF: + info->vboot_workbuf = cbmem_entry->address; + break; + case CBMEM_ID_TIMESTAMP: + info->tstamp_table = cbmem_entry->address; + break; + case CBMEM_ID_VPD: + info->chromeos_vpd = cbmem_entry->address; + break; + case CBMEM_ID_FMAP: + info->fmap_cache = cbmem_entry->address; + break; + case CBMEM_ID_WIFI_CALIBRATION: + info->wifi_calibration = cbmem_entry->address; + break; + case CBMEM_ID_TYPE_C_INFO: + info->type_c_info = cbmem_entry->address; + break; + default: + break; + } +} + int cb_parse_header(void *addr, int len, struct sysinfo_t *info) { struct cb_header *header; @@ -372,33 +373,15 @@ case CB_TAG_VBNV: cb_parse_vbnv(ptr, info); break; - case CB_TAG_VBOOT_WORKBUF: - cb_parse_vboot_workbuf(ptr, info); - break; case CB_TAG_MAC_ADDRS: cb_parse_mac_addresses(ptr, info); break; case CB_TAG_SERIALNO: cb_parse_string(ptr, &info->serialno); break; - case CB_TAG_TIMESTAMPS: - cb_parse_tstamp(ptr, info); - break; - case CB_TAG_CBMEM_CONSOLE: - cb_parse_cbmem_cons(ptr, info); - break; - case CB_TAG_ACPI_GNVS: - cb_parse_acpi_gnvs(ptr, info); - break; - case CB_TAG_ACPI_CNVS: - cb_parse_acpi_cnvs(ptr, info); - break; case CB_TAG_BOARD_CONFIG: cb_parse_board_config(ptr, info); break; - case CB_TAG_WIFI_CALIBRATION: - cb_parse_wifi_calibration(ptr, info); - break; case CB_TAG_RAM_OOPS: cb_parse_ramoops(ptr, info); break; @@ -414,20 +397,14 @@ case CB_TAG_BOOT_MEDIA_PARAMS: cb_parse_boot_media_params(ptr, info); break; + case CB_TAG_CBMEM_ENTRY: + cb_parse_cbmem_entry(ptr, info); + break; #if CONFIG(LP_TIMER_RDTSC) case CB_TAG_TSC_INFO: cb_parse_tsc_info(ptr, info); break; #endif - case CB_TAG_VPD: - cb_parse_vpd(ptr, info); - break; - case CB_TAG_FMAP: - cb_parse_fmap_cache(ptr, info); - break; - case CB_TAG_TYPE_C_INFO: - cb_parse_type_c_info(ptr, info); - break; default: cb_parse_arch_specific(rec, info); break; 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bd02a98ba2631f34014bc0f8e7ebd5a5ddd2321 Gerrit-Change-Number: 59491 Gerrit-PatchSet: 6 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Generate new SPD ID for new memory parts
by Felix Held (Code Review) 03 Dec '21

03 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59642 ) Change subject: mb/google/dedede/var/drawcia: Generate new SPD ID for new memory parts ...................................................................... mb/google/dedede/var/drawcia: Generate new SPD ID for new memory parts Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Samsung K4U6E3S4AA-MGCL BUG=b:204014463 TEST=run part_id_gen to generate SPD id Change-Id: Icb0f211508450b16b2e5d214ae6adc9852718a59 Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59642 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc M src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc index 96284d1..f975bfb 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc @@ -4,4 +4,4 @@ # ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/drawcia/memory src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL, K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt index 78cc95d..8a3c5c8 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt @@ -10,3 +10,4 @@ MT53E512M32D1NP-046 WT:B 0 (0000) H54G46CYRBX267 0 (0000) K4U6E3S4AB-MGCL 0 (0000) +K4U6E3S4AA-MGCL 0 (0000) diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt index f195c25..4a3e217 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt @@ -4,3 +4,4 @@ MT53E512M32D1NP-046 WT:B H54G46CYRBX267 K4U6E3S4AB-MGCL +K4U6E3S4AA-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/59642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb0f211508450b16b2e5d214ae6adc9852718a59 Gerrit-Change-Number: 59642 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: merged

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coreboot-gerrit December 2021