Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58879 )
Change subject: mb/prodrive/hermes: Configure ALC888 port B Vref
......................................................................
mb/prodrive/hermes: Configure ALC888 port B Vref
Define a new field in the board config EEPROM layout for port B Vref.
Write port B Vref settings to unused non-volatile NID 0x12 instead of
NID 0x18, the actual port B NID. Because per-port Vref settings don't
persist after codec resets, a custom Realtek driver (ab)uses NID 0x12
to restore port B Vref after resetting the codec.
Change-Id: Iaa11ba9c74f643e94046d4983fbce65dbedd1025
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58879
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/prodrive/hermes/eeprom.h
M src/mainboard/prodrive/hermes/hda_verb.c
2 files changed, 29 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/prodrive/hermes/eeprom.h b/src/mainboard/prodrive/hermes/eeprom.h
index 26f2faa..a42a3d7 100644
--- a/src/mainboard/prodrive/hermes/eeprom.h
+++ b/src/mainboard/prodrive/hermes/eeprom.h
@@ -51,12 +51,13 @@
uint8_t blue_rear_vref;
uint8_t front_panel_audio;
uint8_t pxe_boot_capability;
+ uint8_t pink_rear_vref;
};
- uint8_t raw_settings[9];
+ uint8_t raw_settings[10];
};
};
-_Static_assert(sizeof(struct eeprom_board_settings) == (9 + sizeof(uint32_t)),
+_Static_assert(sizeof(struct eeprom_board_settings) == (10 + sizeof(uint32_t)),
"struct eeprom_board_settings has invalid size!");
struct __packed eeprom_bmc_settings {
diff --git a/src/mainboard/prodrive/hermes/hda_verb.c b/src/mainboard/prodrive/hermes/hda_verb.c
index 760cecc..7514ce9 100644
--- a/src/mainboard/prodrive/hermes/hda_verb.c
+++ b/src/mainboard/prodrive/hermes/hda_verb.c
@@ -90,6 +90,23 @@
}
}
+static u32 get_port_b_vref_cfg(uint8_t pink_rear_vref)
+{
+ switch (pink_rear_vref) {
+ default:
+ case 0:
+ return 0x411110f0; /* Disabled (Hi-Z) */
+ case 1:
+ return 0x411111f0; /* 50% of LDO out */
+ case 2:
+ return 0x411114f0; /* 80% of LDO out */
+ case 3:
+ return 0x411115f0; /* 100% of LDO out */
+ case 4:
+ return 0x411112f0; /* Ground */
+ }
+}
+
static u32 get_front_panel_cfg(uint8_t front_panel_audio)
{
switch (front_panel_audio) {
@@ -122,7 +139,16 @@
const u32 front_mic_cfg = get_front_mic_cfg(board_cfg->front_panel_audio);
+ const u32 port_b_vref_cfg = get_port_b_vref_cfg(board_cfg->pink_rear_vref);
+
const u32 verbs[] = {
+ /*
+ * Write port B Vref settings to unused non-volatile NID 0x12 instead of
+ * NID 0x18, the actual port B NID. Because per-port Vref settings don't
+ * persist after codec resets, a custom Realtek driver (ab)uses NID 0x12
+ * to restore port B Vref after resetting the codec.
+ */
+ AZALIA_PIN_CFG(0, 0x12, port_b_vref_cfg),
AZALIA_PIN_CFG(0, 0x19, front_mic_cfg),
AZALIA_PIN_CFG(0, 0x1b, front_panel_cfg),
0x0205000d, /* Pin 37 vrefo hidden register - used as port C vref */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iaa11ba9c74f643e94046d4983fbce65dbedd1025
Gerrit-Change-Number: 58879
Gerrit-PatchSet: 5
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59837 )
Change subject: mb/prodrive/hermes: Add board URL
......................................................................
mb/prodrive/hermes: Add board URL
Change-Id: I943d0e2a91778df306f323e2b889cd4e928e0c2b
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59837
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt b/src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt
index 80dba95..009fbfd 100644
--- a/src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt
@@ -1,7 +1,7 @@
Category: server
Vendor name: Prodrive
Board name: Hermes
-Board URL: TBD
+Board URL: https://prodrive-technologies.com/products/embedded-computing-systems/mothe…
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
--
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Gerrit-Change-Id: I943d0e2a91778df306f323e2b889cd4e928e0c2b
Gerrit-Change-Number: 59837
Gerrit-PatchSet: 2
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com>
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59813 )
Change subject: mb/google/guybrush: Configure EN_SPKR GPIO in PSP verstage
......................................................................
mb/google/guybrush: Configure EN_SPKR GPIO in PSP verstage
EN_SPKR GPIO is used as a multiplexer select signal between RAM_ID
straps and Developer Mode Beep signals. During boot up it is LOW and
selects RAM_ID straps. When the system enters OS, it is driven HIGH and
selects DEV BEEP signals. Since in some boards, the GPIO chosen is in S5
domain it does not reset until the system enters mechanical off (G3)
state. On scenarios where the power button is pressed when the system is
in S5, incorrect RAM_ID strap is being read because the EN_SPKR is still
selecting DEV BEEP signal. This causes boot up failures. Fix this by
configuring the EN_SPKR GPIO (in S5 domain) explicitly in PSP verstage.
BUG=b:204450368
TEST=Build and boot to OS in Guybrush. Perform suspend-resume cycle
followed by a S5 -> S0 boot cycle for 2 iterations successfully.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I9a52a167da9c7040731da5d355ec345fd9b13762
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59813
Reviewed-by: Rob Barnes <robbarnes(a)google.com>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/guybrush/variants/guybrush/gpio.c
M src/mainboard/google/guybrush/variants/nipperkin/gpio.c
2 files changed, 4 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Raul Rangel: Looks good to me, approved
Rob Barnes: Looks good to me, approved
diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
index fe2dcd1..0ebee22 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c
+++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
@@ -42,6 +42,8 @@
};
static const struct soc_amd_gpio override_early_gpio_table[] = {
+ /* BID>=2: EN_SPKR to select RAM_ID input, BID < 2: Unused in later stages */
+ PAD_GPO(GPIO_31, LOW),
/* BID == 1: SD_AUX_RESET_L */
PAD_GPO(GPIO_70, LOW),
};
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
index 00fd964..887be83 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
+++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
@@ -40,6 +40,8 @@
static const struct soc_amd_gpio override_early_gpio_table[] = {
PAD_NC(GPIO_18),
+ /* BID==1: EN_SPKR to select RAM_ID input, BID >= 1: Unused in later stages */
+ PAD_GPO(GPIO_31, LOW),
};
static const struct soc_amd_gpio override_pcie_gpio_table[] = {
--
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Gerrit-Change-Id: I9a52a167da9c7040731da5d355ec345fd9b13762
Gerrit-Change-Number: 59813
Gerrit-PatchSet: 3
Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59087 )
Change subject: mb/google/brya/var/brask: Enable LAN driver to program MAC
......................................................................
mb/google/brya/var/brask: Enable LAN driver to program MAC
Turn on the LAN device in devicetree and add Kconfig item
RT8168_GET_MAC_FROM_VPD to support programming MAC address.
BUG=b:193750191
BRANCH=None
TEST=Use 'vpd -s ethernet_mac0=...' to write MAC to VPD.
Use 'ifconfig' to check if the MAC written successfully.
Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59087
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/brask/overridetree.cb
2 files changed, 6 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 6bf1fe1..b14178c 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -8,6 +8,7 @@
def_bool n
select SPD_CACHE_IN_FMAP
select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
+ select RT8168_GET_MAC_FROM_VPD
if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb
index 2122acd..258898d 100644
--- a/src/mainboard/google/brya/variants/brask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brask/overridetree.cb
@@ -79,6 +79,11 @@
device generic 0 alias dptf_policy on end
end
end
+ device ref pcie_rp7 on
+ chip drivers/net
+ device pci 00.0 on end
+ end
+ end # RTL8125 Ethernet NIC
device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 0
register "cpu_pcie_rp[CPU_RP(1)]" = "{
--
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Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59685 )
Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
......................................................................
Patch Set 18:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59685/comment/64b26422_6316d979
PS16, Line 15: 1.
> nit: space after `1. […]
Done
https://review.coreboot.org/c/coreboot/+/59685/comment/26674806_8ea34c32
PS16, Line 20: 2.
> nit: space after `2. […]
Done
https://review.coreboot.org/c/coreboot/+/59685/comment/42f5947e_4791ce37
PS16, Line 25: 1.coreboot will navigate through the CSE region,
: identify the CSE’s NPHY FW version and BIOS NPHY version.
: 2.Compare both versions, if there is a difference, CSE will trigger an
: NPHY FW update. Otherwise, skips the NPHY FW update.
:
: IOM Update:
: 1.coreboot will navigate through the CSE region, identify CSE's IOM
: FW version and BIOS IOM version.
: 2.Compares both versions, if there is a difference, coreboot will
: trigger an IOM FW update.Otherwise, skip IOM FW update.
> same here, spaces after `1. `, etc.
Done
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/59685/comment/11850662_5faa870f
PS16, Line 405:
: __weak bool skip_cse_sub_part_update(void)
: {
: return false;
: }
> I think this makes sense if implementing this function is a rare edge case and most future SoCs usin […]
Done
https://review.coreboot.org/c/coreboot/+/59685/comment/45fb4d68_2c26571d
PS16, Line 805:
> true, the mmap is free
When fmap_locate_area_as_rdev_rw() is used to get the target region device, there is no mmap/munmap callbacks to get the mapping.
https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/refs/he…https://review.coreboot.org/c/coreboot/+/59685/comment/2d49247f_6b2ee747
PS16, Line 959: /* If SOC is not Alderlake A2, skip update */
> Oops missed that one
Done
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/59685/comment/88cdfcde_a71af80e
PS16, Line 343: * Returns true if cse sub-parition update is required otherwise false.
> This should clarify that this is a weak function and what the default behavior is if the platform do […]
Ack
--
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