coreboot-gerrit December 2021

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Change in coreboot[master]: northbridge/amd/pi/00730F01: enable PARALLEL_MP
by Michał Kopeć (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Michał Żygowski, Paul Menzel, Angel Pons, Arthur Heymans. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 ) Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP ...................................................................... Patch Set 10: (2 comments) File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/59808/comment/05e4b649_416d59c6 PS4, Line 874: sysconf_init > > It's also used in `domain_read_resources`. I'm not sure where else this can be moved […] Done File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/59808/comment/eb1f4913_4a3d2bd1 PS8, Line 48: get_node_nums > I'd recommend splitting this off in a separate CL. That will make it easier to review. Split off into CB:59870 -- To view, visit https://review.coreboot.org/c/coreboot/+/59808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Gerrit-Change-Number: 59808 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 03 Dec 2021 14:33:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/beetley: Enable GEO_SAR_ENABLE for beetley
by Patrick Georgi (Code Review) 03 Dec '21

03 Dec '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59544 ) Change subject: mb/google/dedede/var/beetley: Enable GEO_SAR_ENABLE for beetley ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59544/comment/c82d44cd_05987f86 PS3, Line 2: wizard > Hi Pual, […] The downstreaming process from coreboot.org to chromium-review.googlesource.com happens on Google infrastructure so generally speaking people here won't be able to assist you with that. I'm looking into it and will reach out to you. -- To view, visit https://review.coreboot.org/c/coreboot/+/59544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1682cdafe1b6ed7cc0cf23624f83d2e5bbfb92e Gerrit-Change-Number: 59544 Gerrit-PatchSet: 5 Gerrit-Owner: Wizard Shen <shenhu5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Krystal Han <hanlijing(a)huaqin.corp-partner.google.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 14:32:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Wizard Shen <shenhu5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: northbridge/amd/pi/00730F01/northbridge.c: remove unneded global vari...
by Michał Kopeć (Code Review) 03 Dec '21

03 Dec '21

Michał Kopeć has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59870 ) Change subject: northbridge/amd/pi/00730F01/northbridge.c: remove unneded global variables ...................................................................... northbridge/amd/pi/00730F01/northbridge.c: remove unneded global variables Remove global variables `sblink` and `node_nums` and add function `get_node_nums()` which reads from PCI config once returns a static variable. TEST=Boot Debian 11 on PC Engines apu3 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: I20a47f967093ef91355377c164656cabadc30fe6 --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 25 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/59870/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20a47f967093ef91355377c164656cabadc30fe6 Gerrit-Change-Number: 59870 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: northbridge/amd/pi/00730F01/northbridge.c: remove unneded global vari...
by Michał Kopeć (Code Review) 03 Dec '21

03 Dec '21

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59870 ) Change subject: northbridge/amd/pi/00730F01/northbridge.c: remove unneded global variables ...................................................................... northbridge/amd/pi/00730F01/northbridge.c: remove unneded global variables Remove global variables `sblink` and `node_nums`, add function `get_node_nums()` which returns a static variable. TEST=Boot Debian 11 on PC Engines apu3 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: I20a47f967093ef91355377c164656cabadc30fe6 --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 25 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/59870/1 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index b56e9ca..6fc47db 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -29,8 +29,6 @@ #define PCIE_CAP_AER BIT(5) #define PCIE_CAP_ACS BIT(6) -static unsigned int node_nums; -static unsigned int sblink; static struct device *__f0_dev[MAX_NODE_NUMS]; static struct device *__f1_dev[MAX_NODE_NUMS]; static struct device *__f2_dev[MAX_NODE_NUMS]; @@ -42,6 +40,25 @@ return pcidev_on_root(DEV_CDB + nodeid, fn); } +static struct device *get_mc_dev(void) +{ + return pcidev_on_root(DEV_CDB, 0); +} + +static unsigned int get_node_nums(void) +{ + static unsigned int node_nums; + static int already_read; + + if (already_read) + return node_nums; + + node_nums = ((pci_read_config32(get_mc_dev(), 0x60)>>4) & 7) + 1; //NodeCnt[2:0] + already_read = 1; + + return node_nums; +} + static void get_fx_devs(void) { int i; @@ -164,6 +181,9 @@ static void create_vga_resource(struct device *dev, unsigned int nodeid) { struct bus *link; + unsigned int sblink; + + sblink = (pci_read_config32(get_mc_dev(), 0x64)>>8) & 7; // don't forget sublink1 /* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ @@ -724,7 +744,7 @@ int i; mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; - for (i = 0; i < node_nums; i++) { + for (i = 0; i < get_node_nums(); i++) { resource_t basek, limitk; u32 hole; if (!get_dram_base_limit(i, &basek, &limitk)) @@ -742,7 +762,7 @@ */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i = 0; i < node_nums; i++) { + for (i = 0; i < get_node_nums(); i++) { resource_t base_k, limit_k; if (!get_dram_base_limit(i, &base_k, &limit_k)) continue; // no memory on this node @@ -788,7 +808,7 @@ #endif idx = 0x10; - for (i = 0; i < node_nums; i++) { + for (i = 0; i < get_node_nums(); i++) { resource_t basek, limitk, sizek; // 4 1T if (!get_dram_base_limit(i, &basek, &limitk)) @@ -856,24 +876,6 @@ .acpi_name = domain_acpi_name, }; -static void sysconf_init(struct device *dev) // first node -{ - sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 - node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] -} - -static void cpu_bus_scan(struct device *dev) -{ - struct device *dev_mc; - - dev_mc = pcidev_on_root(DEV_CDB, 0); - if (!dev_mc) { - printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); - die(""); - } - sysconf_init(dev_mc); -} - static void pre_mp_init(void) { x86_setup_mtrrs_with_detect(); @@ -906,7 +908,6 @@ .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, - .scan_bus = cpu_bus_scan, }; static void root_complex_enable_dev(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/59870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20a47f967093ef91355377c164656cabadc30fe6 Gerrit-Change-Number: 59870 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/amd/pi/00730F01: enable PARALLEL_MP
by Michał Kopeć (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Michał Żygowski, Michał Kopeć, Paul Menzel, Angel Pons. Hello build bot (Jenkins), Michał Żygowski, Angel Pons, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59808 to look at the new patch set (#10). Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP ...................................................................... northbridge/amd/pi/00730F01: enable PARALLEL_MP Disable LEGACY_SMP_INIT to enable PARALLEL_MP. Also remove a large amount of APIC code that is now unnecessary. TEST=Boot on PC Engines apu3 Inspired by CB:59693 Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/cpu/amd/pi/00730F01/model_16_init.c M src/northbridge/amd/pi/00730F01/Kconfig M src/northbridge/amd/pi/00730F01/northbridge.c 3 files changed, 27 insertions(+), 127 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59808/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/59808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Gerrit-Change-Number: 59808 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] drivers/intel/mipi_camera: Add ACPI entry to provide silicon ty...
by Sugnan Prabhu S (Code Review) 03 Dec '21

03 Dec '21

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59869 ) Change subject: [WIP] drivers/intel/mipi_camera: Add ACPI entry to provide silicon type info ...................................................................... [WIP] drivers/intel/mipi_camera: Add ACPI entry to provide silicon type info Add entry in ACPI table under IPU device to provide silicon type information to IPU driver. IPU driver can decide the type of firmware to load based on this information. BUG=207721978 BRANCH=none TEST=Check for the ACPI entry in the SSDT after booting to kernel Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Change-Id: I4e0af1dd50b9c014cae5454fcd4f9f76d0e0a85f Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c M src/soc/intel/alderlake/Kconfig 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/59869/1 diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index a9af25c..5de0094 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -5,7 +5,9 @@ #include <acpi/acpi_device.h> #include <acpi/acpigen.h> #include <acpi/acpigen_pci.h> +#include <arch/cpu.h> #include <console/console.h> +#include <cpu/intel/cpu_ids.h> #include <device/i2c_simple.h> #include <device/device.h> #include <device/path.h> @@ -101,6 +103,7 @@ struct acpi_dp *port_table = NULL; struct acpi_dp *remote = NULL; struct acpi_dp *lanes = NULL; + u32 cpu_id; for (i = 0; i < config->cio2_num_ports && i < MAX_PORT_ENTRIES; ++i) { snprintf(name, sizeof(name), "EP%u0", i); @@ -134,6 +137,14 @@ snprintf(name, sizeof(name), "port%u", i); port_name[i] = strdup(name); + if (CONFIG(ACPI_ADL_IPU_ES_SUPPORT)) { + cpu_id = cpu_get_cpuid(); + if (cpu_id == CPUID_ALDERLAKE_A0 || cpu_id == CPUID_ALDERLAKE_A1) + acpi_dp_add_integer(dsd, "is_es", 1); + else + acpi_dp_add_integer(dsd, "is_es", 0); + } + acpi_dp_add_child(dsd, port_name[i], port_table); } diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 2f8f3da..151fe73 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -22,6 +22,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_ADL_IPU_ES_SUPPORT select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS @@ -328,6 +329,11 @@ help Enables CrashLog. +config ACPI_ADL_IPU_ES_SUPPORT + def_bool n + help + Enables support for ES silicon ACPI entry for IPU. + if STITCH_ME_BIN config CSE_BPDT_VERSION -- To view, visit https://review.coreboot.org/c/coreboot/+/59869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e0af1dd50b9c014cae5454fcd4f9f76d0e0a85f Gerrit-Change-Number: 59869 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib: Fix edge case of log2_ceil()
by Paul Menzel (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Julius Werner, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59834 ) Change subject: lib: Fix edge case of log2_ceil() ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59834/comment/ac4a9bc8_9526f027 PS2, Line 7: lib: Fix edge case of log2_ceil() Be specific: > lib: Fix log2_ceil() for 0xffffffff -- To view, visit https://review.coreboot.org/c/coreboot/+/59834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If868f793b909a6ad7fc48a7affac15e2c714fa2e Gerrit-Change-Number: 59834 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 13:53:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Define soc_get_pcie_rp_type
by Paul Menzel (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59853 ) Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59853/comment/31fa0bef_4ed37860 PS1, Line 10: tigerlake Nit: Tiger Lake -- To view, visit https://review.coreboot.org/c/coreboot/+/59853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Gerrit-Change-Number: 59853 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 13:52:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Fix edge case of log2_ceil()
by Paul Menzel (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Julius Werner, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59834 ) Change subject: lib: Fix edge case of log2_ceil() ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If868f793b909a6ad7fc48a7affac15e2c714fa2e Gerrit-Change-Number: 59834 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 03 Dec 2021 13:38:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for ADL-N CPU Type
by Paul Menzel (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Reka Norman, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Usha P, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59836 ) Change subject: soc/intel/alderlake: Add support for ADL-N CPU Type ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59836/comment/5015f2ce_23635631 PS2, Line 9: This patch is intended to add This patch adds … or Add … -- To view, visit https://review.coreboot.org/c/coreboot/+/59836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d Gerrit-Change-Number: 59836 Gerrit-PatchSet: 2 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 13:37:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021