coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/brya:[TEST_ONLY] Run Mem frequency @ lowest Speed
by Sridhar Siricilla (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. Sridhar Siricilla has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/59862 ) Change subject: mb/google/brya:[TEST_ONLY] Run Mem frequency @ lowest Speed ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/59862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbc591aff89e166bf90c0cec8bd308f8ea5a47dd Gerrit-Change-Number: 59862 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/alderlake:[TEST_ONLY] Disable SaGv
by Sridhar Siricilla (Code Review) 03 Dec '21

03 Dec '21

Sridhar Siricilla has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/59864 ) Change subject: soc/intel/alderlake:[TEST_ONLY] Disable SaGv ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/59864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1335dd2ef304ba9ab97ce5c5889875ade691239c Gerrit-Change-Number: 59864 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/alderlake:[TEST_ONLY] Disable SaGv
by Sridhar Siricilla (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Patrick Rudolph. Sridhar Siricilla has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/59864 ) Change subject: soc/intel/alderlake:[TEST_ONLY] Disable SaGv ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/59864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1335dd2ef304ba9ab97ce5c5889875ade691239c Gerrit-Change-Number: 59864 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: amdfwtool: Add options to separate signed firmwares
by Kangheui Won (Code Review) 03 Dec '21

03 Dec '21

Kangheui Won has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59866 ) Change subject: amdfwtool: Add options to separate signed firmwares ...................................................................... amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another file. If sig_opt in file header is 1 it means that the firmware is signed by AMD and will be verified by the PSP. If we put them outside FW_MAIN_[AB] we can skip vboot verification on them, improving overall verification time. BUG=b:206909680 TEST=build amdfwtool Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 171 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/59866/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Gerrit-Change-Number: 59866 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Add options to separate signed firmwares
by build bot (Jenkins) (Code Review) 03 Dec '21

03 Dec '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59866 ) Change subject: amdfwtool: Add options to separate signed firmwares ...................................................................... Patch Set 1: (3 comments) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134891): https://review.coreboot.org/c/coreboot/+/59866/comment/a0550d98_7134ae5a PS1, Line 645: signed_rom_fd = open(signed_rom , O_RDWR | O_CREAT | O_TRUNC, 0666); space prohibited before that ',' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134891): https://review.coreboot.org/c/coreboot/+/59866/comment/5d71a0a0_cf246b80 PS1, Line 646: if (signed_rom_fd < 0) { suspect code indent for conditional statements (8, 24) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134891): https://review.coreboot.org/c/coreboot/+/59866/comment/2f406bba_b2c3bcb7 PS1, Line 696: fprintf(stderr, "failed to allocate memory with size %lld\n", (long long)fd_stat.st_size); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/59866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Gerrit-Change-Number: 59866 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Dec 2021 11:28:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Separate signed amdfw
by Kangheui Won (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59867 ) Change subject: mb/google/guybrush: Separate signed amdfw ...................................................................... mb/google/guybrush: Separate signed amdfw Put signed amd firmwares into SIGNED_AMDFW_[AB] region which is outside FW_MAIN_[AB]. Vboot only verifies FW_MAIN_[AB] so these regions will not be verified by vboot; instead the PSP will verify them. As a result we have less to load and verify from SPI rom which means faster boot time. BUG=b:206909680 TEST=build & boot guybrush, observed ~60ms boot time improvements Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: If4fd3cff11a38d82afb8c5ce379f1d1b5b9adfbf --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/chromeos.fmd M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc 4 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/59867/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index c97c06d..066f437 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -54,6 +54,10 @@ bool "Enable PSP_verstage" default y if VBOOT +config SEPARATE_SIGNED_AMDFW + bool "Separate signed amd fw from FW_MAIN region" + default y if VBOOT + config VBOOT_STARTS_IN_BOOTBLOCK bool default y if VBOOT && !VBOOT_STARTS_BEFORE_BOOTBLOCK diff --git a/src/mainboard/google/guybrush/chromeos.fmd b/src/mainboard/google/guybrush/chromeos.fmd index 3875700..5c80e9f 100644 --- a/src/mainboard/google/guybrush/chromeos.fmd +++ b/src/mainboard/google/guybrush/chromeos.fmd @@ -2,11 +2,13 @@ SI_BIOS { RW_MRC_CACHE(PRESERVE) 64K RW_SECTION_A 3M { + SIGNED_AMDFW_A 1M VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 256 } RW_SECTION_B 3M { + SIGNED_AMDFW_B 1M VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 256 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 6c8c3e5..f618876 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -458,6 +458,12 @@ Add a space-delimited list of filenames that should only be in the RW-B section. +config SEPARATE_SIGNED_AMDFW + def_bool n + help + Put signed amd firmwares outside FW_MAIN_[AB] + so vboot doesn't verify them and rely on AMD's verification. + endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK endif # SOC_AMD_CEZANNE diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 58df740..cd3ba39 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -151,6 +151,13 @@ PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK +ifeq ($(CONFIG_SEPARATE_SIGNED_AMDFW),y) +SIGNED_AMDFW_A_POSITION=$(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_A_START" {print $$3}' $(obj)/fmap_config.h) +SIGNED_AMDFW_B_POSITION=$(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_B_START" {print $$3}' $(obj)/fmap_config.h) +SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed +SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed +endif # CONFIG_SEPARATE_SIGNED_AMDFW + # Helper function to return a value with given bit set # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. set-bit=$(call int-shift-left, 1 $(call _toint,$1)) @@ -184,6 +191,11 @@ OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) +OPT_SIGNED_AMDFW_A_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_A_POSITION), --signed-addr) +OPT_SIGNED_AMDFW_A_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_A_FILE), --signed-output) +OPT_SIGNED_AMDFW_B_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_B_POSITION), --signed-addr) +OPT_SIGNED_AMDFW_B_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_B_FILE), --signed-output) + OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) @@ -247,6 +259,8 @@ $(AMDFW_COMMON_ARGS) \ $(OPT_APOB_NV_SIZE) \ $(OPT_APOB_NV_BASE) \ + $(OPT_SIGNED_AMDFW_A_POSITION) \ + $(OPT_SIGNED_AMDFW_A_FILE) \ --location $(shell printf "%#x" $(CEZANNE_FW_A_POSITION)) \ --anywhere \ --multilevel \ @@ -259,6 +273,8 @@ $(AMDFW_COMMON_ARGS) \ $(OPT_APOB_NV_SIZE) \ $(OPT_APOB_NV_BASE) \ + $(OPT_SIGNED_AMDFW_B_POSITION) \ + $(OPT_SIGNED_AMDFW_B_FILE) \ --location $(shell printf "%#x" $(CEZANNE_FW_B_POSITION)) \ --anywhere \ --multilevel \ @@ -280,6 +296,12 @@ apu/amdfw_b-file := $(obj)/amdfw_b.rom apu/amdfw_b-position := $(call strip_quotes, $(CEZANNE_FW_B_POSITION)) apu/amdfw_b-type := raw + +ifeq ($(CONFIG_SEPARATE_SIGNED_AMDFW),y) +build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.signed +endif # CONFIG_SEPARATE_SIGNED_AMDFW endif cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) -- To view, visit https://review.coreboot.org/c/coreboot/+/59867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4fd3cff11a38d82afb8c5ce379f1d1b5b9adfbf Gerrit-Change-Number: 59867 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Add options to separate signed firmwares
by Kangheui Won (Code Review) 03 Dec '21

03 Dec '21

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59866 ) Change subject: amdfwtool: Add options to separate signed firmwares ...................................................................... amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another file. If sig_opt in file header is 1 it means that the firmware is signed by AMD and will be verified by the PSP. If we put them outside FW_MAIN_[AB] we can skip vboot verification on them, improving overall verification time. BUG=b:206909680 TEST=build amdfwtool Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 170 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/59866/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index ee360f0..856aa6f 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -630,6 +630,117 @@ } } +static void process_signed_psp_firmwares(const char *signed_rom, + amd_fw_entry *fw_table, + uint64_t signed_start_addr) +{ + unsigned int i; + int fd; + int signed_rom_fd; + ssize_t bytes; + uint8_t *buf; + struct amd_fw_header header; + struct stat fd_stat; + + signed_rom_fd = open(signed_rom , O_RDWR | O_CREAT | O_TRUNC, 0666); + if (signed_rom_fd < 0) { + fprintf(stderr, "Error opening file: %s: %s\n", + signed_rom, strerror(errno)); + return; + } + + for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + if (!(fw_table[i].filename)) + continue; + + memset(&header, 0, sizeof(header)); + + fd = open(fw_table[i].filename, O_RDONLY); + if (fd < 0) { + fprintf(stderr, "Error opening file: %s: %s\n", + fw_table[i].filename, strerror(errno)); + continue; + } + + if (fstat(fd, &fd_stat)) { + fprintf(stderr, "fstat error: %s\n", strerror(errno)); + close(fd); + continue; + } + + bytes = read(fd, &header, sizeof(struct amd_fw_header)); + if (bytes < (ssize_t)sizeof(struct amd_fw_header)) { + close(fd); + continue; + } + + /* If firmware header looks like invalid, assume it's not signed */ + if (!header.fw_type) { + close(fd); + continue; + } + + if (header.size_total != fd_stat.st_size) { + close(fd); + continue; + } + + if (header.sig_opt != 1) { + close(fd); + continue; + } + + buf = malloc(fd_stat.st_size); + + if (!buf) { + fprintf(stderr, "failed to allocate memory with size %lld\n", (long long)fd_stat.st_size); + close(fd); + continue; + } + + lseek(fd, SEEK_SET, 0); + bytes = read(fd, buf, fd_stat.st_size); + + if (bytes != fd_stat.st_size) { + fprintf(stderr, "failed to read : %lld %lld\n", + (long long)bytes, (long long)fd_stat.st_size); + free(buf); + close(fd); + continue; + } + + bytes = write(signed_rom_fd, buf, fd_stat.st_size); + + /* if failed to write, try again */ + if (bytes != fd_stat.st_size) { + ssize_t bytes2; + if (bytes < 0) + bytes = 0; + bytes2 = write(signed_rom_fd, buf + bytes, fd_stat.st_size - bytes); + + /* if failed again, give up and rewind file */ + if (bytes + bytes2 != fd_stat.st_size) { + if (bytes2 < 0) + bytes2 = 0; + lseek(signed_rom_fd, SEEK_CUR, -(bytes + bytes2)); + free(buf); + close(fd); + continue; + } + } + + fw_table[i].addr_signed = signed_start_addr; + fw_table[i].file_size = (uint32_t)fd_stat.st_size; + + signed_start_addr += fd_stat.st_size; + + free(buf); + close(fd); + } + + close(signed_rom_fd); +} + static void integrate_psp_firmwares(context *ctx, psp_directory_table *pspdir, psp_directory_table *pspdir2, @@ -709,21 +820,26 @@ BLOB_ERASE_ALIGNMENT); count++; } else if (fw_table[i].filename != NULL) { - bytes = copy_blob(BUFF_CURRENT(*ctx), - fw_table[i].filename, BUFF_ROOM(*ctx)); - if (bytes < 0) { - free(ctx->rom); - exit(1); + if (fw_table[i].addr_signed) { + pspdir->entries[count].addr = fw_table[i].addr_signed; + bytes = fw_table[i].file_size; + } else { + bytes = copy_blob(BUFF_CURRENT(*ctx), + fw_table[i].filename, BUFF_ROOM(*ctx)); + if (bytes < 0) { + free(ctx->rom); + exit(1); + } + pspdir->entries[count].addr = RUN_CURRENT(*ctx); + ctx->current = ALIGN(ctx->current + bytes, + BLOB_ALIGNMENT); } pspdir->entries[count].type = fw_table[i].type; pspdir->entries[count].subprog = fw_table[i].subprog; pspdir->entries[count].rsvd = 0; pspdir->entries[count].size = (uint32_t)bytes; - pspdir->entries[count].addr = RUN_CURRENT(*ctx); - ctx->current = ALIGN(ctx->current + bytes, - BLOB_ALIGNMENT); count++; } else { /* This APU doesn't have this firmware. */ @@ -1046,6 +1162,9 @@ AMDFW_OPT_SHAREDMEM, AMDFW_OPT_SHAREDMEM_SIZE, AMDFW_OPT_SOC_NAME, + + AMDFW_OPT_SIGNED_OUTPUT, + AMDFW_OPT_SIGNED_ADDR, /* begin after ASCII characters */ LONGOPT_SPI_READ_MODE = 256, LONGOPT_SPI_SPEED = 257, @@ -1096,6 +1215,9 @@ {"sharedmem-size", required_argument, 0, AMDFW_OPT_SHAREDMEM_SIZE }, {"soc-name", required_argument, 0, AMDFW_OPT_SOC_NAME }, + {"signed-output", required_argument, 0, AMDFW_OPT_SIGNED_OUTPUT }, + {"signed-addr", required_argument, 0, AMDFW_OPT_SIGNED_ADDR }, + {"config", required_argument, 0, AMDFW_OPT_CONFIG }, {"debug", no_argument, 0, AMDFW_OPT_DEBUG }, {"help", no_argument, 0, AMDFW_OPT_HELP }, @@ -1291,6 +1413,9 @@ uint8_t efs_spi_speed = 0xff; uint8_t efs_spi_micron_flag = 0xff; + const char *signed_output_file = NULL; + uint64_t signed_start_addr = 0x0; + amd_cb_config cb_config; int debug = 0; int list_deps = 0; @@ -1423,6 +1548,14 @@ } sub = instance = 0; break; + case AMDFW_OPT_SIGNED_OUTPUT: + signed_output_file = optarg; + sub = instance = 0; + break; + case AMDFW_OPT_SIGNED_ADDR: + signed_start_addr = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; case LONGOPT_SPI_READ_MODE: efs_spi_readmode = strtoull(optarg, NULL, 16); sub = instance = 0; @@ -1602,6 +1735,11 @@ ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ + if (signed_output_file && signed_start_addr) + process_signed_psp_firmwares(signed_output_file, + amd_psp_fw_table, + signed_start_addr); + if (cb_config.multi_level) { /* Do 2nd PSP directory followed by 1st */ psp_directory_table *pspdir2 = new_psp_dir(&ctx, cb_config.multi_level); diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index a7ac7c1..07c4760 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -218,8 +218,32 @@ uint8_t subprog; int level; uint64_t other; + uint64_t addr_signed; + uint32_t file_size; } amd_fw_entry; +struct amd_fw_header { + uint8_t reserved_0[20]; + uint32_t fw_size_signed; + uint8_t reserved_18[24]; + /* 1 if the image is signed, 0 otherwise */ + uint32_t sig_opt; + uint32_t sig_id; + uint8_t sig_param[16]; + uint32_t comp_opt; + uint8_t reserved_4c[4]; + uint32_t uncomp_size; + uint32_t comp_size; + uint8_t reserved_58[20]; + uint32_t size_total; + uint8_t reserved_70[12]; + uint8_t fw_type; + uint8_t fw_subtype; + uint8_t fw_subprog; + uint8_t reserved_7f; + uint8_t reserved_80[128]; +} __attribute__((packed)); + typedef struct _amd_cb_config { bool have_whitelist; bool unlock_secure; -- To view, visit https://review.coreboot.org/c/coreboot/+/59866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Gerrit-Change-Number: 59866 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64)
by Arthur Heymans (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Subrata Banik, Wonkyu Kim, Mariusz Szafrański, Jonathan Zhang, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Tim Chu, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59744 ) Change subject: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64) ...................................................................... Patch Set 7: (1 comment) File src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/59744/comment/b37509d0_482940cf PS7, Line 192: Note: This ought to be VOID*, but that won't allow calling this binary on x86_64. not up to date anymore ;-) -- To view, visit https://review.coreboot.org/c/coreboot/+/59744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If12b63a282c660da6f57fe23b0b848e2d155853f Gerrit-Change-Number: 59744 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Dec 2021 11:07:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64)
by Arthur Heymans (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Subrata Banik, Wonkyu Kim, Mariusz Szafrański, Jonathan Zhang, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Tim Chu, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59744 ) Change subject: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64) ...................................................................... Patch Set 7: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/59744/comment/fc959eff_60d19e22 PS6, Line 41: uint64_t > it looks only address related parameters are changed to 64bit. > Can we use uintptr_t instead of conditional definition? > I think if we use uintptr_t it can work for both 32bit and 64bit. I prefer clear fixed length types when dealing with external binary headers. -- To view, visit https://review.coreboot.org/c/coreboot/+/59744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If12b63a282c660da6f57fe23b0b848e2d155853f Gerrit-Change-Number: 59744 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Dec 2021 11:05:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: northbridge/amd/pi/00730F01: enable PARALLEL_MP
by Michał Kopeć (Code Review) 03 Dec '21

03 Dec '21

Attention is currently required from: Michał Żygowski, Michał Kopeć, Paul Menzel, Angel Pons. Hello build bot (Jenkins), Michał Żygowski, Angel Pons, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59808 to look at the new patch set (#9). Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP ...................................................................... northbridge/amd/pi/00730F01: enable PARALLEL_MP Disable LEGACY_SMP_INIT to enable PARALLEL_MP. Also remove a large amount of APIC code that is now unnecessary. TEST=Boot on PC Engines apu3 Inspired by CB:59693 Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/cpu/amd/pi/00730F01/model_16_init.c M src/northbridge/amd/pi/00730F01/Kconfig M src/northbridge/amd/pi/00730F01/northbridge.c 3 files changed, 45 insertions(+), 144 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59808/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/59808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Gerrit-Change-Number: 59808 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021