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Change subject: soc/intel/common: Rename compare_cse_version() function name
......................................................................
Patch Set 9: Code-Review+1
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Hello build bot (Jenkins), Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59826
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Change subject: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake
......................................................................
soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake
Check the Alderlake CPU ID to determine if cse sub-paritition update is
required or not.
Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
---
M src/soc/intel/alderlake/romstage/romstage.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/59826/3
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Hello Marx Wang, build bot (Jenkins), Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Balaji Manigandan, Nick Vaccaro, Kane Chen, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
......................................................................
soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
This patch adds the following support to coreboot
1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B
partition of BIOS
2. Helper functions to support update.
Pre-requisites to enable IOM/NPHY FW Update:
1. NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and
FW_MAIN_B through board configuration files.
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path
SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path
2. Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition
NPHY/IOM update.
coreboot follows below procedure to update NPHY and IOM:
NPHY Update:
1. coreboot will navigate through the CSE region,
identify the CSE’s NPHY FW version and BIOS NPHY version.
2. Compare both versions, if there is a difference, CSE will trigger an
NPHY FW update. Otherwise, skips the NPHY FW update.
IOM Update:
1. coreboot will navigate through the CSE region, identify CSE's IOM
FW version and BIOS IOM version.
2. Compares both versions, if there is a difference, coreboot will
trigger an IOM FW update.Otherwise, skip IOM FW update.
Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT
PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE
boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only
if CSE boots from CSE RO Boot partition.
Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then
triggers update of NPHY and IOM FW in the CSE Region(RO and RW).
coreboot triggers NPHY/IOM update procedure in all ChromeOS boot
modes(Normal and Recovery).
BUG=b:202143532
BRANCH=None
TEST=Build and verify CSE sub-partitions IOM and NPHY are getting
updated with CBFS IOM and NPHY blobs.
Verified TBT, type-C display, NVMe, SD card, WWAN, Wifi working after
the update.
Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
A src/soc/intel/common/block/include/intelblocks/cse_layout.h
5 files changed, 454 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/59685/17
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Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Krishna P Bhat D, Kane Chen, Patrick Rudolph.
Krishna P Bhat D has uploaded a new patch set (#7) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/59698 )
Change subject: soc/intel/common: Add check before sending HMRFPO_ENABLE command
......................................................................
soc/intel/common: Add check before sending HMRFPO_ENABLE command
This patch adds a check to determine if the CSE's current operation mode
is ME_HFS1_COM_SECOVER_MEI_MSG or not before sending HMRFPO_ENABLE command
to CSE. If CSE is already in the ME_HFS1_COM_SECOVER_MEI_MSG, coreboot
skips sending HMRFPO_ENABLE command to CSE to unlock the CSE RW
partition.
TEST=Verify sending HMRFPO_ENABLE command on Brya system.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/59698/7
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59477 )
Change subject: soc/amd/cezanne: Enable secure counters
......................................................................
soc/amd/cezanne: Enable secure counters
Guybrush uses secure counters to protect against High Definition (HD)
protected content rollback. These secure counters are hosted in TPM
NVRAM. Enable secure counters so that they are defined in PSP verstage.
BUG=b:205261728
TEST=Build and boot to OS in Guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM.
Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59477
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Rob Barnes <robbarnes(a)google.com>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
Rob Barnes: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index b4e808d..df37a82 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -72,6 +72,7 @@
select SOC_AMD_COMMON_FSP_PCI
select SSE2
select UDK_2017_BINDING
+ select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
select X86_AMD_FIXED_MTRRS
select X86_INIT_NEED_1_SIPI
5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59476 )
Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM
......................................................................
src/security/vboot: Set up secure counter space in TPM NVRAM
High Definition (HD) protected content playback requires secure counters
that are updated at regular interval while the protected content is
playing. To support similar use-cases, define space for secure counters
in TPM NVRAM and initialize them. These counters are defined once during
the factory initialization stage. Also add
VBOOT_DEFINE_WIDEVINE_COUNTERS config item to enable these secure
counters only on the mainboard where they are required/used.
BUG=b:205261728
TEST=Build and boot to OS in guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM space.
tlcl_define_space: response is 0
tlcl_define_space: response is 0
tlcl_define_space: response is 0
tlcl_define_space: response is 0
On reboot if forced to redefine the space, it is identified as already
defined.
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59476
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
M src/security/vboot/Kconfig
M src/security/vboot/antirollback.h
M src/security/vboot/secdata_tpm.c
3 files changed, 43 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Julius Werner: Looks good to me, approved
Raul Rangel: Looks good to me, approved
diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig
index 7cbeea3..26f2484 100644
--- a/src/security/vboot/Kconfig
+++ b/src/security/vboot/Kconfig
@@ -282,6 +282,14 @@
Use sha256msg1, sha256msg2, sha256rnds2 instruction to accelerate
SHA hash calculation in vboot.
+config VBOOT_DEFINE_WIDEVINE_COUNTERS
+ bool
+ default n
+ help
+ Set up Widevine Secure Counters in TPM NVRAM by defining space. Enabling this
+ config will only define the counter space. Counters need to be incremented
+ separately before any read operation is performed on them.
+
menu "GBB configuration"
config GBB_HWID
diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h
index 2297762..71605fa 100644
--- a/src/security/vboot/antirollback.h
+++ b/src/security/vboot/antirollback.h
@@ -29,6 +29,11 @@
#define MRC_RW_HASH_NV_INDEX 0x100d
#define HASH_NV_SIZE VB2_SHA256_DIGEST_SIZE
#define ENT_ROLLBACK_COUNTER_INDEX 0x100e
+/* Widevine Secure Counter space */
+#define WIDEVINE_COUNTER_NV_INDEX(n) (0x3000 + (n))
+#define NUM_WIDEVINE_COUNTERS 4
+#define WIDEVINE_COUNTER_NAME "Widevine Secure Counter"
+#define WIDEVINE_COUNTER_SIZE sizeof(uint64_t)
/* Zero-Touch Enrollment related spaces */
#define ZTE_BOARD_ID_NV_INDEX 0x3fff00
#define ZTE_RMA_SN_BITS_INDEX 0x3fff01
diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c
index 47efe2d..6d8e281 100644
--- a/src/security/vboot/secdata_tpm.c
+++ b/src/security/vboot/secdata_tpm.c
@@ -158,6 +158,18 @@
.TPMA_NV_POLICY_DELETE = 1,
};
+static const TPMA_NV rw_orderly_counter_attributes = {
+ .TPMA_NV_COUNTER = 1,
+ .TPMA_NV_ORDERLY = 1,
+ .TPMA_NV_AUTHREAD = 1,
+ .TPMA_NV_AUTHWRITE = 1,
+ .TPMA_NV_PLATFORMCREATE = 1,
+ .TPMA_NV_WRITE_STCLEAR = 1,
+ .TPMA_NV_PPREAD = 1,
+ .TPMA_NV_PPWRITE = 1,
+ .TPMA_NV_NO_DA = 1,
+};
+
/*
* This policy digest was obtained using TPM2_PolicyOR on 3 digests
* corresponding to a sequence of
@@ -350,6 +362,19 @@
rw_counter_attributes, NULL, 0);
}
+static uint32_t setup_widevine_counter_spaces(void)
+{
+ uint32_t index, rv;
+
+ for (index = 0; index < NUM_WIDEVINE_COUNTERS; index++) {
+ rv = define_space(WIDEVINE_COUNTER_NAME, WIDEVINE_COUNTER_NV_INDEX(index),
+ WIDEVINE_COUNTER_SIZE, rw_orderly_counter_attributes, NULL, 0);
+ if (rv != TPM_SUCCESS)
+ return rv;
+ }
+ return TPM_SUCCESS;
+}
+
static uint32_t _factory_initialize_tpm(struct vb2_context *ctx)
{
RETURN_ON_FAILURE(tlcl_force_clear());
@@ -391,6 +416,11 @@
if (CONFIG(CHROMEOS))
RETURN_ON_FAILURE(enterprise_rollback_create_counter());
+ /* Define widevine counter space. No need to increment/write to the secure counters
+ and are expected to be incremented during the first use. */
+ if (CONFIG(VBOOT_DEFINE_WIDEVINE_COUNTERS))
+ RETURN_ON_FAILURE(setup_widevine_counter_spaces());
+
RETURN_ON_FAILURE(setup_firmware_space(ctx));
return TPM_SUCCESS;
--
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Attention is currently required from: Kangheui Won, Isaac Lee, Reka Norman, chris wang, Felix Held.
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59558 )
Change subject: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/zork/variants/shuboz/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/59558/comment/7b1efcee_80ff7512
PS5, Line 2: fw_config
> Ok, so IIUC based on your comment in https://crrev. […]
Thanks for your help, I modify the setting of "probe" according to the CL you provided, both devices can works from SSFC setting.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59870
to look at the new patch set (#3).
Change subject: northbridge/amd/pi/00730F01/northbridge.c: remove unneded global variables
......................................................................
northbridge/amd/pi/00730F01/northbridge.c: remove unneded global variables
Remove global variables `sblink` and `node_nums` and add function
`get_node_nums()` which reads from PCI config once returns a static variable.
TEST=Boot Debian 11 on PC Engines apu3
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Change-Id: I20a47f967093ef91355377c164656cabadc30fe6
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/northbridge/amd/pi/00730F01/northbridge.c
1 file changed, 23 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/59870/3
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Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59836 )
Change subject: soc/intel/alderlake: Add support for ADL-N CPU Type
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59836/comment/b3e58781_0888bc75
PS2, Line 9: This patch is intended to add
> This patch adds … […]
Done
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Hello build bot (Jenkins), Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Reka Norman, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59836
to look at the new patch set (#3).
Change subject: soc/intel/alderlake: Add support for ADL-N CPU Type
......................................................................
soc/intel/alderlake: Add support for ADL-N CPU Type
Add Alder Lake-N case for adl_cpu_type and get_supported_lpm_mask.
Signed-off-by: Usha P <usha.p(a)intel.com>
Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d
---
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/include/soc/cpu.h
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/59836/3
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