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Change subject: soc/intel/common/pch: Fix the comment typos for CHIPSET_LOCKDOWN
......................................................................
Patch Set 3: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59857/comment/2169cf69_19c858b3
PS3, Line 2: JingleHsuWiwynn
Jingle Hsu
$ git config --global user.name "Jingle Hsu"
$ git commit --amend --author="Jingle Hsu <jingle_hsu(a)wiwynn.com>"
https://review.coreboot.org/c/coreboot/+/59857/comment/8c56669b_3d734345
PS3, Line 7: Fix the comment typos for CHIPSET_LOCKDOWN
Maybe:
> Fix return value documentation for CHIPSET_LOCKDOWN
https://review.coreboot.org/c/coreboot/+/59857/comment/a92954c7_f0b17c21
PS3, Line 12: JingleHsuWiwynn
Ditto.
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Change subject: tests: Disable -Wmain-return-type for clang
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59815/comment/bc4719b7_bbd1d620
PS1, Line 13: clang
Please document the clang version you hit this with.
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Change subject: mb/google/dedede/var/magolor: Add fw_config probe for multi codec and amplifier
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Patch Set 2: Code-Review+1
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Change subject: mb/google/guybrush: Separate signed amdfw
......................................................................
Patch Set 2:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59867/comment/6ae53064_cd568fb5
PS2, Line 13: which means
: faster boot time
I’d mention the 60 ms here too.
That’s quite some improvement. How big is the AMD firmware? Why does it take so long?
Patchset:
PS2:
It’d be great, if you split the SOC and mainboard changes into separate commits.
File src/soc/amd/cezanne/Kconfig:
https://review.coreboot.org/c/coreboot/+/59867/comment/131b827a_1a48eed4
PS2, Line 464: amd
AMD
https://review.coreboot.org/c/coreboot/+/59867/comment/c774dfad_e8f602f7
PS2, Line 465: them and
Comma after *them*?
https://review.coreboot.org/c/coreboot/+/59867/comment/aed752f5_f688ee3b
PS2, Line 465: rely on AMD's verification
… in PSP?
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Change subject: tests: Fix objcopy --add-symbol arguments creation
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/alderlake, soc/common: Add method to determine the cpu type
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Hmm, we haven't made it very easy to get data out of MP Init, have we.... […]
We can't avoid the returns/fills an array of core types even we put entire procedure in a single function. The array generation is important to map CPU index to CPU type in the ascending order since OS consumes this information(CPPC3 package) and populate CPU's specific structure in the same order.
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Change subject: soc/intel/alderlake:[TEST_ONLY] Run Mem Controller @ lowest frequency
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59862
to look at the new patch set (#3).
Change subject: soc/intel/alderlake:[TEST_ONLY] Run Mem Controller @ lowest frequency
......................................................................
soc/intel/alderlake:[TEST_ONLY] Run Mem Controller @ lowest frequency
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: Ibbc591aff89e166bf90c0cec8bd308f8ea5a47dd
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/59862/3
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