Change in coreboot[master]: soc/intel/tigerlake: Define soc_get_pcie_rp_type

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Patrick Rudolph.
Hello build bot (Jenkins), Paul Menzel, Subrata Banik, Patrick Rudolph, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/59853

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type
......................................................................

soc/intel/tigerlake: Define soc_get_pcie_rp_type

In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Tiger Lake.

BUG=b:197983574

Signed-off-by: Tim Wawrzynczak <[e-mail]>
Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620
---
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
M src/soc/intel/tigerlake/Makefile.inc
A src/soc/intel/tigerlake/pcie_rp.c
3 files changed, 56 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59853/3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620
Gerrit-Change-Number: 59853
Gerrit-PatchSet: 3
Gerrit-Owner: Tim Wawrzynczak <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: Paul Menzel <[e-mail]>
Gerrit-Reviewer: Subrata Banik <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-Attention: Patrick Rudolph <[e-mail]>
Gerrit-MessageType: newpatchset