Change in coreboot[master]: soc/intel/alderlake: Define soc_get_pcie_rp_type

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Subrata Banik, Patrick Rudolph.
Hello build bot (Jenkins), Subrata Banik, Patrick Rudolph, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/59854

to look at the new patch set (#3).

Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type
......................................................................

soc/intel/alderlake: Define soc_get_pcie_rp_type

In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Alder Lake. While we're
here, add PCIe RP group definitions for PCH-M chipsets.

BUG=b:197983574

Signed-off-by: Tim Wawrzynczak <[e-mail]>
Change-Id: I7438513e10b7cea8dac678b97a901b710247c188
---
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/pcie_rp.c
3 files changed, 54 insertions(+), 1 deletion(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59854/3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7438513e10b7cea8dac678b97a901b710247c188
Gerrit-Change-Number: 59854
Gerrit-PatchSet: 3
Gerrit-Owner: Tim Wawrzynczak <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: Subrata Banik <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-CC: Paul Menzel <[e-mail]>
Gerrit-Attention: Subrata Banik <[e-mail]>
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Gerrit-MessageType: newpatchset