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Change in coreboot[master]: util/sconfig: Change __pci*|__pnp* device pointers to const
by Nico Huber (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Furquan Shaikh, Martin Roth. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49242 ) Change subject: util/sconfig: Change __pci*|__pnp* device pointers to const ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I061b05d994fc5c4156ee8bddabadf940f0aeeac3 Gerrit-Change-Number: 49242 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 18:32:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Enable TC Cold support
by Srinidhi N Kaushik (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Patrick Rudolph. Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Enable TC Cold support ...................................................................... soc/intel/tigerlake: Enable TC Cold support This change enables support for TC cold usb connect. BUG=b:173054070 TEST=Build and boot on delbin. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/49244/1 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 295f789..2a6a41c 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -134,6 +134,9 @@ */ params->ITbtConnectTopologyTimeoutInMs = 0; + /* Enable TcColdOnUsbConnect */ + params->DisableTccoldOnUsbConnected = 0; + /* Chipset Lockdown */ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { params->PchLockDownGlobalSmi = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
by Srinidhi N Kaushik (Code Review) 08 Jan '21

08 Jan '21

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49243 ) Change subject: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers ...................................................................... vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers Update v 3444 FSP headers for Tiger Lake platform to include the below 2 UPDs to control TC cold support usb connect or not. FSPS: Usb3ComplModeEnable DisableTccoldOnUsbConnected Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I68b32730293fc83b5088074f71fa215220574748 --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 1 file changed, 20 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/49243/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 276ac79..e791115 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -931,7 +931,17 @@ /** Offset 0x04BA - Reserved **/ - UINT8 Reserved20[7]; + UINT8 Reserved20[2]; + +/** Offset 0x04BC - Disable TC code On USB Connect + Enable(default) or Disable TC cold On Usb Connected + $EN_DIS +**/ + UINT8 DisableTccoldOnUsbConnected; + +/** Offset 0x04BD - Reserved +**/ + UINT8 Reserved21[4]; /** Offset 0x04C1 - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable @@ -965,7 +975,7 @@ /** Offset 0x04C6 - Reserved **/ - UINT8 Reserved21; + UINT8 Reserved22; /** Offset 0x04C7 - VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default) @@ -975,7 +985,7 @@ /** Offset 0x04C8 - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved23; /** Offset 0x04C9 - VMD Mem Bar1 Attributes 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH @@ -985,7 +995,7 @@ /** Offset 0x04CA - Reserved **/ - UINT8 Reserved23; + UINT8 Reserved24; /** Offset 0x04CB - VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH @@ -1001,7 +1011,7 @@ /** Offset 0x04CD - Reserved **/ - UINT8 Reserved24; + UINT8 Reserved25; /** Offset 0x04CE - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides @@ -1048,9 +1058,11 @@ **/ UINT8 VccSt; -/** Offset 0x04DD - Reserved +/** Offset 0x04DD - TCSS Usb3 Compliance Mode Enable + Used by IOM FW to skip powering down the PHY at the end of disconnect flow + $EN_DIS **/ - UINT8 Reserved25; + UINT8 Usb3ComplModeEnable; /** Offset 0x04DE - ITBT DMA LTR TCSS DMA1, DMA2 LTR value -- To view, visit https://review.coreboot.org/c/coreboot/+/49243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68b32730293fc83b5088074f71fa215220574748 Gerrit-Change-Number: 49243 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Nico Huber (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Tim Crawford, Jeremy Soller, Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 6: Code-Review+2 (2 comments) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/56b03520_5e783ae3 PS6, Line 531: * use the table. It seems a bit stale now, update at will. https://review.coreboot.org/c/coreboot/+/49104/comment/48f0f5c8_6ca3d5e3 PS6, Line 558: = {0} Initialization is not required anymore. And actually never was, `static` storage class is always 0. -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 18:29:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Change __pci*|__pnp* device pointers to const
by Furquan Shaikh (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Martin Roth. Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49242 ) Change subject: util/sconfig: Change __pci*|__pnp* device pointers to const ...................................................................... util/sconfig: Change __pci*|__pnp* device pointers to const This change updates the device pointers exposed in static_devices.h to const instead of DEVTREE_CONST. The pointer itself doesn't really need to be DEVTREE_CONST. Change-Id: I061b05d994fc5c4156ee8bddabadf940f0aeeac3 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/sconfig/main.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/49242/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 175b926..1af55ac 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1211,16 +1211,16 @@ { /* Only devices on root bus here. */ if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) { - fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d;\n", + fprintf(head, "extern DEVTREE_CONST struct device *const __pci_0_%02x_%d;\n", ptr->path_a, ptr->path_b); - fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d = &%s;\n", + fprintf(fil, "DEVTREE_CONST struct device *const __pci_0_%02x_%d = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); } if (ptr->bustype == PNP) { - fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x;\n", + fprintf(head, "extern DEVTREE_CONST struct device *const __pnp_%04x_%02x;\n", ptr->path_a, ptr->path_b); - fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x = &%s;\n", + fprintf(fil, "DEVTREE_CONST struct device *const __pnp_%04x_%02x = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/49242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I061b05d994fc5c4156ee8bddabadf940f0aeeac3 Gerrit-Change-Number: 49242 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA
by Clay Daniels (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Nico Huber, Felix Held. Clay Daniels has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49241 ) Change subject: superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: Nico, the only datasheet I had was for the NCT6791D. I see you seem to have written line 541 to show the NANA entries. What do I need to do next? File util/superiotool/nuvoton.c: https://review.coreboot.org/c/coreboot/+/49241/comment/b903f732_61173e86 PS1, Line 541: 0x7f,NANA,0x00,NANA, > For instance: […] Nico, the only datasheet I had was for the NCT6791D. I see you seem to have written line 541 to show the NANA entries. What do I need to do next? -- To view, visit https://review.coreboot.org/c/coreboot/+/49241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3 Gerrit-Change-Number: 49241 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Clay Daniels <clay.daniels.jr(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Jan 2021 17:07:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Update ec_commands.h
by Yu-Ping Wu (Code Review) 08 Jan '21

08 Jan '21

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49196 ) Change subject: ec/google/chromeec: Update ec_commands.h ...................................................................... ec/google/chromeec: Update ec_commands.h This change copies ec_commands.h directly from the Chromium OS EC repo at SHA afffc28f2, with the exception of changing the copyright header to SPDX format. Change-Id: Ie02e0295312050e803a7d701ec4eed1dadfa6c9a Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/ec/google/chromeec/ec_commands.h 1 file changed, 342 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/49196/1 diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index fb83d60..39e1cec 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -29,7 +29,10 @@ #include "compile_time_macros.h" #else +/* If BUILD_ASSERT isn't already defined, make it a no-op */ +#ifndef BUILD_ASSERT #define BUILD_ASSERT(_cond) +#endif /* !BUILD_ASSERT */ #endif /* CHROMIUM_EC */ #ifdef __KERNEL__ @@ -50,6 +53,21 @@ #define BIT_ULL(nr) (1ULL << (nr)) #endif +/* + * When building Zephyr, this file ends up being included before Zephyr's + * include/sys/util.h so causes a warning there. We don't want to add an #ifdef + * in that file since it won't be accepted upstream. So work around it here. + */ +#ifndef CONFIG_ZEPHYR +#ifndef GENMASK +#define GENMASK(h, l) (((BIT(h) << 1) - 1) ^ (BIT(l) - 1)) +#endif + +#ifndef GENMASK_ULL +#define GENMASK_ULL(h, l) (((BIT_ULL(h) << 1) - 1) ^ (BIT_ULL(l) - 1)) +#endif +#endif + #endif /* __KERNEL__ */ /* @@ -1388,7 +1406,7 @@ */ EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, /* - * Early Firmware Selection ver.2. Enabled by VBOOT_EFS2 config option. + * Early Firmware Selection ver.2. Enabled by CONFIG_VBOOT_EFS2. * Note this is a RO feature. So, a query (EC_CMD_GET_FEATURES) should * be sent to RO to be precise. */ @@ -1397,6 +1415,18 @@ EC_FEATURE_SCP = 39, /* The MCU is an Integrated Sensor Hub */ EC_FEATURE_ISH = 40, + /* New TCPMv2 TYPEC_ prefaced commands supported */ + EC_FEATURE_TYPEC_CMD = 41, + /* + * The EC will wait for direction from the AP to enter Type-C alternate + * modes or USB4. + */ + EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY = 42, + /* + * The EC will wait for an acknowledge from the AP after setting the + * mux. + */ + EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43, }; #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) @@ -2599,6 +2629,11 @@ MOTIONSENSE_ORIENTATION_UNKNOWN = 4, }; +struct ec_response_activity_data { + uint8_t activity; /* motionsensor_activity */ + uint8_t state; +} __ec_todo_packed; + struct ec_response_motion_sensor_data { /* Flags for each sensor. */ uint8_t flags; @@ -2606,17 +2641,16 @@ uint8_t sensor_num; /* Each sensor is up to 3-axis. */ union { - int16_t data[3]; + int16_t data[3]; /* for sensors using unsigned data */ - uint16_t udata[3]; + uint16_t udata[3]; struct __ec_todo_packed { - uint16_t reserved; - uint32_t timestamp; + uint16_t reserved; + uint32_t timestamp; }; struct __ec_todo_unpacked { - uint8_t activity; /* motionsensor_activity */ - uint8_t state; - int16_t add_info[2]; + struct ec_response_activity_data activity_data; + int16_t add_info[2]; }; }; } __ec_todo_packed; @@ -2864,8 +2898,19 @@ /* Ignored, used for alignment. */ uint8_t reserved; - /* Individual component values to spoof. */ - int16_t components[3]; + union { + /* Individual component values to spoof. */ + int16_t components[3]; + + /* Used when spoofing an activity */ + struct { + /* enum motionsensor_activity */ + uint8_t activity_num; + + /* spoof activity state */ + uint8_t activity_state; + }; + }; } spoof; /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ @@ -3768,6 +3813,7 @@ #define EC_MKBP_LID_OPEN 0 #define EC_MKBP_TABLET_MODE 1 #define EC_MKBP_BASE_ATTACHED 2 +#define EC_MKBP_FRONT_PROXIMITY 3 /* Run keyboard factory test scanning */ #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 @@ -4637,6 +4683,7 @@ EC_DEVICE_EVENT_TRACKPAD, EC_DEVICE_EVENT_DSP, EC_DEVICE_EVENT_WIFI, + EC_DEVICE_EVENT_WLC, }; enum ec_device_event_param { @@ -5183,6 +5230,7 @@ EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_IDLE flag */ + EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */ }; /* Flags for ec_params_reboot_ec.reboot_flags */ @@ -5395,10 +5443,6 @@ /* Active Link Uni-Direction */ #define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) -/* - * Underdevelopement : - * Please remove this tag if using _v2 outside platform/ec - */ struct ec_response_usb_pd_control_v2 { uint8_t enabled; uint8_t role; @@ -5408,8 +5452,7 @@ uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ uint8_t reserved; /* Reserved for future use */ uint8_t control_flags; /* USB_PD_CTRL_*flags */ - /* TODO: b:158234949 Add definitions for cable speed */ - uint8_t cable_speed; /* USB_R30_SS/TBT_SS_* cable speed */ + uint8_t cable_speed; /* TBT_SS_* cable speed */ uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ } __ec_align1; @@ -5833,7 +5876,7 @@ */ #define EC_CMD_GET_UPTIME_INFO 0x0121 -/* Reset causes */ +/* EC reset causes */ #define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */ #define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */ #define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */ @@ -5862,6 +5905,72 @@ #define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ #define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ +/* + * Reason codes used by the AP after a shutdown to figure out why it was reset + * by the EC. These are sent in EC commands. Therefore, to maintain protocol + * compatibility: + * - New entries must be inserted prior to the _COUNT field + * - If an existing entry is no longer in service, it must be replaced with a + * RESERVED entry instead. + * - The semantic meaning of an entry should not change. + * - Do not exceed 2^15 - 1 for reset reasons or 2^16 - 1 for shutdown reasons. + */ +enum chipset_reset_reason { + CHIPSET_RESET_BEGIN = 0, + CHIPSET_RESET_UNKNOWN = CHIPSET_RESET_BEGIN, + /* Custom reason defined by a board.c or baseboard.c file */ + CHIPSET_RESET_BOARD_CUSTOM, + /* Believe that the AP has hung */ + CHIPSET_RESET_HANG_REBOOT, + /* Reset by EC console command */ + CHIPSET_RESET_CONSOLE_CMD, + /* Reset by EC host command */ + CHIPSET_RESET_HOST_CMD, + /* Keyboard module reset key combination */ + CHIPSET_RESET_KB_SYSRESET, + /* Keyboard module warm reboot */ + CHIPSET_RESET_KB_WARM_REBOOT, + /* Debug module warm reboot */ + CHIPSET_RESET_DBG_WARM_REBOOT, + /* I cannot self-terminate. You must lower me into the steel. */ + CHIPSET_RESET_AP_REQ, + /* Reset as side-effect of startup sequence */ + CHIPSET_RESET_INIT, + /* EC detected an AP watchdog event. */ + CHIPSET_RESET_AP_WATCHDOG, + + CHIPSET_RESET_COUNT, +}; + +/* + * AP hard shutdowns are logged on the same path as resets. + */ +enum chipset_shutdown_reason { + CHIPSET_SHUTDOWN_BEGIN = BIT(15), + CHIPSET_SHUTDOWN_POWERFAIL = CHIPSET_SHUTDOWN_BEGIN, + /* Forcing a shutdown as part of EC initialization */ + CHIPSET_SHUTDOWN_INIT, + /* Custom reason on a per-board basis. */ + CHIPSET_SHUTDOWN_BOARD_CUSTOM, + /* This is a reason to inhibit startup, not cause shut down. */ + CHIPSET_SHUTDOWN_BATTERY_INHIBIT, + /* A power_wait_signal is being asserted */ + CHIPSET_SHUTDOWN_WAIT, + /* Critical battery level. */ + CHIPSET_SHUTDOWN_BATTERY_CRIT, + /* Because you told me to. */ + CHIPSET_SHUTDOWN_CONSOLE_CMD, + /* Forcing a shutdown to effect entry to G3. */ + CHIPSET_SHUTDOWN_G3, + /* Force shutdown due to over-temperature. */ + CHIPSET_SHUTDOWN_THERMAL, + /* Force a chipset shutdown from the power button through EC */ + CHIPSET_SHUTDOWN_BUTTON, + + CHIPSET_SHUTDOWN_COUNT, +}; + + struct ec_response_uptime_info { /* * Number of milliseconds since the last EC boot. Sysjump resets @@ -5889,10 +5998,7 @@ /* Empty log entries have both the cause and timestamp set to zero. */ struct ap_reset_log_entry { - /* - * See include/chipset.h: enum chipset_{reset,shutdown}_reason - * for details. - */ + /* See enum chipset_{reset,shutdown}_reason for details. */ uint16_t reset_cause; /* Reserved for protocol growth. */ @@ -6012,13 +6118,21 @@ * * This command is used for validation purpose, where the AP needs to be * returned back to S0 state from G3 state without using the servo to trigger - * wake events.For this,there is no request or response struct. - * - * Order of command usage: - * ectool reboot_ap_on_g3 && shutdown -h now + * wake events. + * - With command version 0: + * AP reboots immediately from G3 + * command usage: ectool reboot_ap_on_g3 && shutdown -h now + * - With command version 1: + * AP reboots after the user specified delay + * command usage: ectool reboot_ap_on_g3 [<delay>] && shutdown -h now */ #define EC_CMD_REBOOT_AP_ON_G3 0x0127 +struct ec_params_reboot_ap_on_g3_v1 { + /* configurable delay in seconds in G3 state */ + uint32_t reboot_ap_at_g3_delay; +} __ec_align4; + /*****************************************************************************/ /* Get PD port capabilities * @@ -6366,6 +6480,14 @@ enum typec_control_command { TYPEC_CONTROL_COMMAND_EXIT_MODES, TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, + TYPEC_CONTROL_COMMAND_ENTER_MODE, +}; + +/* Modes (USB or alternate) that a type-C port may enter. */ +enum typec_mode { + TYPEC_MODE_DP, + TYPEC_MODE_TBT, + TYPEC_MODE_USB4, }; struct ec_params_typec_control { @@ -6380,6 +6502,7 @@ */ union { uint32_t clear_events_mask; + uint8_t mode_to_enter; /* enum typec_mode */ uint8_t placeholder[128]; }; } __ec_align1; @@ -6393,9 +6516,6 @@ * EC_CMD_USB_PD_CONTROL command. * * This also combines in the EC_CMD_USB_PD_MUX_INFO flags. - * - * Version 0 of command is under development - * TODO(b/167700356): Remove this statement when version 0 is finalized */ #define EC_CMD_TYPEC_STATUS 0x0133 @@ -6469,33 +6589,183 @@ #define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) #define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) +/* + * Encode and decode for BCD revision response + * + * Note: the major revision set is written assuming that the value given is the + * Specification Revision from the PD header, which currently only maps to PD + * 1.0-3.0 with the major revision being one greater than the binary value. + */ +#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12) +#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF) +#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF) + +/* + * Decode helpers for Source and Sink Capability PDOs + * + * Note: The Power Delivery Specification should be considered the ultimate + * source of truth on the decoding of these PDOs + */ +#define PDO_TYPE_FIXED (0 << 30) +#define PDO_TYPE_BATTERY (1 << 30) +#define PDO_TYPE_VARIABLE (2 << 30) +#define PDO_TYPE_AUGMENTED (3 << 30) +#define PDO_TYPE_MASK (3 << 30) + +/* + * From Table 6-9 and Table 6-14 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Fixed Supply + * <29> : Dual-Role Power + * <28> : SNK/SRC dependent + * <27> : Unconstrained Power + * <26> : USB Communications Capable + * <25> : Dual-Role Data + * <24:20> : SNK/SRC dependent + * <19:10> : Voltage in 50mV Units + * <9:0> : Maximum Current in 10mA units + */ +#define PDO_FIXED_DUAL_ROLE BIT(29) +#define PDO_FIXED_UNCONSTRAINED BIT(27) +#define PDO_FIXED_COMM_CAP BIT(26) +#define PDO_FIXED_DATA_SWAP BIT(25) +#define PDO_FIXED_FRS_CURR_MASK GENMASK(24, 23) /* Sink Cap only */ +#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10) + +/* + * From Table 6-12 and Table 6-16 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Battery + * <29:20> : Maximum Voltage in 50mV units + * <19:10> : Minimum Voltage in 50mV units + * <9:0> : Maximum Allowable Power in 250mW units + */ +#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250) + +/* + * From Table 6-11 and Table 6-15 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Variable Supply (non-Battery) + * <29:20> : Maximum Voltage in 50mV units + * <19:10> : Minimum Voltage in 50mV units + * <9:0> : Operational Current in 10mA units + */ +#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10) + +/* + * From Table 6-13 and Table 6-17 PD Rev 3.0 Ver 2.0 + * + * Note this type is reserved in PD 2.0, and only one type of APDO is + * supported as of the cited version. + * + * <31:30> : Augmented Power Data Object + * <29:28> : Programmable Power Supply + * <27> : PPS Power Limited + * <26:25> : Reserved + * <24:17> : Maximum Voltage in 100mV increments + * <16> : Reserved + * <15:8> : Minimum Voltage in 100mV increments + * <7> : Reserved + * <6:0> : Maximum Current in 50mA increments + */ +#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100) +#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100) +#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50) + struct ec_params_typec_status { uint8_t port; } __ec_align1; struct ec_response_typec_status { - uint8_t pd_enabled; /* PD communication enabled - bool */ - uint8_t dev_connected; /* Device connected - bool */ - uint8_t sop_connected; /* Device is SOP PD capable - bool */ - uint8_t reserved1; /* Reserved for future use */ + uint8_t pd_enabled; /* PD communication enabled - bool */ + uint8_t dev_connected; /* Device connected - bool */ + uint8_t sop_connected; /* Device is SOP PD capable - bool */ + uint8_t source_cap_count; /* Number of Source Cap PDOs */ - uint8_t power_role; /* enum pd_power_role */ - uint8_t data_role; /* enum pd_data_role */ - uint8_t vconn_role; /* enum pd_vconn_role */ - uint8_t reserved2; /* Reserved for future use */ + uint8_t power_role; /* enum pd_power_role */ + uint8_t data_role; /* enum pd_data_role */ + uint8_t vconn_role; /* enum pd_vconn_role */ + uint8_t sink_cap_count; /* Number of Sink Cap PDOs */ - uint8_t polarity; /* enum tcpc_cc_polarity */ - uint8_t cc_state; /* enum pd_cc_states */ - uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ - uint8_t mux_state; /* USB_PD_MUX* - encoded USB mux state */ + uint8_t polarity; /* enum tcpc_cc_polarity */ + uint8_t cc_state; /* enum pd_cc_states */ + uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ + uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */ - char tc_state[32]; /* TC state name */ + char tc_state[32]; /* TC state name */ - uint32_t events; /* PD_STATUS_EVENT bitmask */ + uint32_t events; /* PD_STATUS_EVENT bitmask */ - /* TODO(b/167700356): Add revisions and source cap PDOs */ + /* + * BCD PD revisions for partners + * + * The format has the PD major reversion in the upper nibble, and PD + * minor version in the next nibble. Following two nibbles are + * currently 0. + * ex. PD 3.2 would map to 0x3200 + * + * PD major/minor will be 0 if no PD device is connected. + */ + uint16_t sop_revision; + uint16_t sop_prime_revision; + + uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */ + + uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */ } __ec_align1; +/** + * Get the number of peripheral charge ports + */ +#define EC_CMD_PCHG_COUNT 0x0134 + +#define EC_PCHG_MAX_PORTS 8 + +struct ec_response_pchg_count { + uint8_t port_count; +} __ec_align1; + +/** + * Get the status of a peripheral charge port + */ +#define EC_CMD_PCHG 0x0135 + +struct ec_params_pchg { + uint8_t port; +} __ec_align1; + +struct ec_response_pchg { + uint32_t error; /* enum pchg_error */ + uint8_t state; /* enum pchg_state state */ + uint8_t battery_percentage; +} __ec_align2; + +enum pchg_state { + /* Charger is reset and not initialized. */ + PCHG_STATE_RESET = 0, + /* Charger is initialized or disabled. */ + PCHG_STATE_INITIALIZED, + /* Charger is enabled and ready to detect a device. */ + PCHG_STATE_ENABLED, + /* Device is detected in proximity. */ + PCHG_STATE_DETECTED, + /* Device is being charged. */ + PCHG_STATE_CHARGING, +}; + +#define EC_PCHG_STATE_TEXT { \ + [PCHG_STATE_RESET] = "RESET", \ + [PCHG_STATE_INITIALIZED] = "INITIALIZED", \ + [PCHG_STATE_ENABLED] = "ENABLED", \ + [PCHG_STATE_DETECTED] = "DETECTED", \ + [PCHG_STATE_CHARGING] = "CHARGING", \ + } + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ @@ -6841,6 +7111,28 @@ uint32_t cycle_count; } __ec_align4; +/** + * struct ec_response_battery_static_info_v1 - hostcmd v1 battery static info + * Equivalent to struct ec_response_battery_static_info, but with longer + * strings. + * @design_capacity: battery design capacity (in mAh) + * @design_voltage: battery design voltage (in mV) + * @cycle_count: battery cycle count + * @manufacturer_ext: battery manufacturer string + * @model_ext: battery model string + * @serial_ext: battery serial number string + * @type_ext: battery type string + */ +struct ec_response_battery_static_info_v1 { + uint16_t design_capacity; + uint16_t design_voltage; + uint32_t cycle_count; + char manufacturer_ext[12]; + char model_ext[12]; + char serial_ext[12]; + char type_ext[12]; +} __ec_align4; + /* * Get battery dynamic information, i.e. information that is likely to change * every time it is read. @@ -6896,6 +7188,13 @@ uint8_t allow_charging; } __ec_align_size1; +/* Get ACK from the USB-C SS muxes */ +#define EC_CMD_USB_PD_MUX_ACK 0x0603 + +struct ec_params_usb_pd_mux_ack { + uint8_t port; /* USB-C port number */ +} __ec_align1; + /*****************************************************************************/ /* * Reserve a range of host commands for board-specific, experimental, or -- To view, visit https://review.coreboot.org/c/coreboot/+/49196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie02e0295312050e803a7d701ec4eed1dadfa6c9a Gerrit-Change-Number: 49196 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA
by Nico Huber (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Clay Daniels, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49241 ) Change subject: superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA ...................................................................... Patch Set 1: (1 comment) File util/superiotool/nuvoton.c: https://review.coreboot.org/c/coreboot/+/49241/comment/894adefa_9d6778b8 PS1, Line 541: 0x7f,NANA,0x00,NANA, For instance: 0xe0 (GPIO7 I/O register) configures all GPIOs as inputs (bit 7 is reserved). Hence, the values of 0xe1 (GPIO7 Data) and 0xe3 (GPIO7 Status) depend on these inputs (from other mainboard components) and can't be predicted. -- To view, visit https://review.coreboot.org/c/coreboot/+/49241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3 Gerrit-Change-Number: 49241 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Clay Daniels <clay.daniels.jr(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Clay Daniels <clay.daniels.jr(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Jan 2021 16:18:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA
by Nico Huber (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Clay Daniels, Felix Held. Hello Clay Daniels, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/49241 to review the following change. Change subject: superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA ...................................................................... superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA There were several default values given for GPIO data and status registers. As all GPIO are configured as inputs by default, we can't predict the values of these registers, hence set their default values to NANA. Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/superiotool/nuvoton.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/49241/1 diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index d2b72f2..ffd12be 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -538,13 +538,13 @@ {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, {0x07, "GPIO 6, GPIO 7, GPIO 8", {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xec,0xed,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, - {0x00,0x7f,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x00,0x7f,NANA,0x00,NANA,0xff,NANA,0x00,NANA,0x00,0x00,0xff,NANA,0x00,NANA,0x00,EOT}}, {0x08, "WDT1, WDT_MEM, GPIO 0, GPIO 1", {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfe,0xff,EOT}, - {0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x00,0x00,0x00,0xff,NANA,0x00,NANA,0x00,0xff,NANA,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {0x09, "GPIO 2, GPIO 3, GPIO 4, GPIO 5", {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4,0xf5,0xf6,0xf7,0xfe,EOT}, - {0x00,0xff,0x00,0x00,0x00,0x7f,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x00,0xff,NANA,0x00,NANA,0x7f,NANA,0x00,NANA,NANA,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0xff,NANA,0x00,NANA,0x00,EOT}}, {0x0a, "ACPI", {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9,0xec,0xed,0xee,0xf0,0xf2,0xf3,0xf4,0xf6,0xf7,0xfc,0xfe,EOT}, {0x01,0x00,0x00,0x00,0x00,0x02,0x1a,0x00,0x00,0x00,0x00,0x00,0x10,0x5c,0x00,0x00,0x00,0xc0,0x00,0x00,EOT}}, -- To view, visit https://review.coreboot.org/c/coreboot/+/49241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3 Gerrit-Change-Number: 49241 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Clay Daniels <clay.daniels.jr(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Clay Daniels <clay.daniels.jr(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Generate GNB IO-APIC PCI routing table
by Raul Rangel (Code Review) 08 Jan '21

08 Jan '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48668 ) Change subject: soc/amd/picasso: Generate GNB IO-APIC PCI routing table ...................................................................... soc/amd/picasso: Generate GNB IO-APIC PCI routing table This adds support for generating a PCI routing table that routes to the GNB IO-APIC. This means we no longer need to route to the FCH IO-APIC for PCI interrupts. BUG=b:170595019 TEST=Boot ezkinil to OS with `pci=nomsi amd_iommu=off` and verify all peripherals are working CPU0 CPU1 0: 112 0 IO-APIC 2-edge timer 1: 0 99 IO-APIC 1-edge i8042 4: 0 2523 IO-APIC 4-edge ttyS0 5: 34632 0 IO-APIC 5-fasteoi mmc1 7: 5646 0 IO-APIC 7-fasteoi pinctrl_amd 8: 0 0 IO-APIC 8-edge rtc0 9: 0 33 IO-APIC 9-fasteoi acpi 10: 88258 0 IO-APIC 10-edge AMD0010:00 11: 0 32485 IO-APIC 11-edge AMD0010:01 24: 3301 0 amd_gpio 3 cr50_i2c 25: 0 235214 IO-APIC 28-fasteoi amdgpu 26: 67408 0 IO-APIC 31-fasteoi xhci-hcd:usb1 27: 0 488876 IO-APIC 8-fasteoi mmc0 28: 1265 0 amd_gpio 9 PNP0C50:00 29: 656 0 amd_gpio 12 ELAN9004:00 30: 413 0 amd_gpio 31 chromeos-ec 31: 14153 0 IO-APIC 4-fasteoi ath10k_pci 32: 2 0 sysfstrig0 cros-ec-accel_consumer3 33: 2 0 sysfstrig0 cros-ec-accel_consumer0 34: 6 0 amd_gpio 62 rt5682 35: 0 38937 IO-APIC 29-fasteoi snd_hda_intel:card0, ACP3x_I2S_IRQ Cq-Depend: chrome-internal:3452710 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I3211ab351a332fafb7b5f9ef486bb6646d9a214c --- M src/soc/amd/picasso/pcie_gpp.c 1 file changed, 100 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/48668/1 diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index ca368f9..8b6af4a 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpigen.h> +#include <arch/ioapic.h> #include <assert.h> #include <amdblocks/amd_pci_util.h> #include <device/device.h> @@ -139,9 +140,36 @@ } acpigen_write_method("_PRT", 0); + + /* If (PMOD) */ + acpigen_write_if(); + acpigen_emit_namestring("PMOD"); + + /* Return (Package{...}) */ acpigen_emit_byte(RETURN_OP); - acpigen_write_package(4); + acpigen_write_package(4); /* Package - APIC Routing */ + for (unsigned int i = 0; i < 4; ++i) { + irq_index = calculate_irq(pci_routing, i); + + acpigen_write_package(4); + acpigen_write_dword(0x0000FFFF); + acpigen_write_byte(i); + acpigen_write_byte(0); /* Source: GSI */ + /* GNB IO-APIC is located after the FCH IO-APIC */ + acpigen_write_dword(IO_APIC_INTERRUPTS + irq_index); + acpigen_pop_len(); + } + acpigen_pop_len(); /* Package - APIC Routing */ + acpigen_pop_len(); /* End If */ + + /* Else */ + acpigen_write_else(); + + /* Return (Package{...}) */ + acpigen_emit_byte(RETURN_OP); + + acpigen_write_package(4); /* Package - PIC Routing */ for (unsigned int i = 0; i < 4; ++i) { irq_index = calculate_irq(pci_routing, i); @@ -154,7 +182,9 @@ acpigen_write_dword(0); acpigen_pop_len(); } - acpigen_pop_len(); /* Package */ + acpigen_pop_len(); /* Package - PIC Routing */ + + acpigen_pop_len(); /* End Else */ acpigen_pop_len(); /* Method */ } @@ -174,40 +204,80 @@ * * Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table * { - * Return (Package (0x04) + * If (PMOD) * { - * Package (0x04) + * Return (Package (0x04) * { - * 0x0000FFFF, - * 0x00, - * \_SB.INTE, - * 0x00000000 - * }, + * Package (0x04) + * { + * 0x0000FFFF, + * 0x00, + * 0x00, + * 0x00000034 + * }, * - * Package (0x04) - * { - * 0x0000FFFF, - * 0x01, - * \_SB.INTF, - * 0x00000000 - * }, + * Package (0x04) + * { + * 0x0000FFFF, + * 0x01, + * 0x00, + * 0x00000035 + * }, * - * Package (0x04) - * { - * 0x0000FFFF, - * 0x02, - * \_SB.INTG, - * 0x00000000 - * }, + * Package (0x04) + * { + * 0x0000FFFF, + * 0x02, + * 0x00, + * 0x00000036 + * }, * - * Package (0x04) + * Package (0x04) + * { + * 0x0000FFFF, + * 0x03, + * 0x00, + * 0x00000037 + * } + * }) + * } + * Else + * { + * Return (Package (0x04) * { - * 0x0000FFFF, - * 0x03, - * \_SB.INTH, - * 0x00000000 - * } - * }) + * Package (0x04) + * { + * 0x0000FFFF, + * 0x00, + * \_SB.INTE, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x01, + * \_SB.INTF, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x02, + * \_SB.INTG, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x03, + * \_SB.INTH, + * 0x00000000 + * } + * }) + * } * } * } * } -- To view, visit https://review.coreboot.org/c/coreboot/+/48668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3211ab351a332fafb7b5f9ef486bb6646d9a214c Gerrit-Change-Number: 48668 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2021