Attention is currently required from: Tim Crawford, Jeremy Soller, Angel Pons.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 )
Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
......................................................................
Patch Set 6: Code-Review+2
(2 comments)
File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/49104/comment/56b03520_5e783ae3
PS6, Line 531: * use the table.
It seems a bit stale now, update at will.
https://review.coreboot.org/c/coreboot/+/49104/comment/48f0f5c8_6ca3d5e3
PS6, Line 558: = {0}
Initialization is not required anymore. And actually never was, `static`
storage class is always 0.
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