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Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/49104/comment/929c5558_c49cea42
PS6, Line 531: * use the table.
> What about it do you consider stale?
The last sentence seemed to imply that we would still add that dummy entry.
But reading it again, it's generally true, so nothing to do.
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Change subject: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
......................................................................
Patch Set 3: Code-Review+2
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Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 )
Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/49104/comment/dfae7431_af1ef857
PS6, Line 531: * use the table.
> It seems a bit stale now, update at will.
What about it do you consider stale?
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Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49245 )
Change subject: soc/amd/cezzane: Add a minimal chipset tree
......................................................................
soc/amd/cezzane: Add a minimal chipset tree
This change adds a minimal chipset tree with only two devices:
1. Domain
2. GNB root complex
This allows sconfig to generate the config structure for SoC root
device that is used by config_of_soc().
Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/amd/cezanne/Kconfig
A src/soc/amd/cezanne/chipset.cb
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/49245/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index cb613e3..4e0f4c8 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -25,6 +25,10 @@
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
+config CHIPSET_DEVICETREE
+ string
+ default "soc/amd/cezanne/chipset.cb"
+
config EARLY_RESERVED_DRAM_BASE
hex
default 0x2000000
diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb
new file mode 100644
index 0000000..49bd0c8
--- /dev/null
+++ b/src/soc/amd/cezanne/chipset.cb
@@ -0,0 +1,5 @@
+chip soc/amd/cezanne
+ device domain 0 on
+ device pci 00.0 alias gnb on end
+ end
+end
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Change subject: soc/intel/tigerlake: Enable TC Cold support
......................................................................
Patch Set 2: Code-Review+1
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Change subject: soc/intel/tigerlake: Enable TC Cold support
......................................................................
Patch Set 2: Code-Review+1
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Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49243
to look at the new patch set (#3).
Change subject: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
......................................................................
vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
Update v 3444 FSP headers for Tiger Lake platform to include the
below 2 UPDs to control TC cold support usb connect or not.
FSPS:
Usb3ComplModeEnable
DisableTccoldOnUsbConnected
BUG=b:173054070
TEST=Build and boot on delbin.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com>
Change-Id: I68b32730293fc83b5088074f71fa215220574748
---
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
1 file changed, 20 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/49243/3
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Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49243
to look at the new patch set (#2).
Change subject: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
......................................................................
vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
Update v 3444 FSP headers for Tiger Lake platform to include the
below 2 UPDs to control TC cold support usb connect or not.
FSPS:
Usb3ComplModeEnable
DisableTccoldOnUsbConnected
BUG=b:173054070
TEST=Build and boot on delbin.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com>
Change-Id: I68b32730293fc83b5088074f71fa215220574748
---
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
1 file changed, 20 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/49243/2
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