coreboot-gerrit January 2021

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Change in coreboot[master]: soc/amd/cezzane: Add a minimal chipset tree
by Furquan Shaikh (Code Review) 08 Jan '21

08 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49245 ) Change subject: soc/amd/cezzane: Add a minimal chipset tree ...................................................................... soc/amd/cezzane: Add a minimal chipset tree This change adds a minimal chipset tree with only two devices: 1. Domain 2. GNB root complex This allows sconfig to generate the config structure for SoC root device that is used by config_of_soc(). Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/chipset.cb 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/49245/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index cb613e3..4e0f4c8 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -25,6 +25,10 @@ select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H +config CHIPSET_DEVICETREE + string + default "soc/amd/cezanne/chipset.cb" + config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb new file mode 100644 index 0000000..49bd0c8 --- /dev/null +++ b/src/soc/amd/cezanne/chipset.cb @@ -0,0 +1,5 @@ +chip soc/amd/cezanne + device domain 0 on + device pci 00.0 alias gnb on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/49245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f Gerrit-Change-Number: 49245 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Enable TC Cold support
by John Zhao (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, John Zhao, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Enable TC Cold support ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 08 Jan 2021 19:20:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
by John Zhao (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, John Zhao, Dossym Nurmukhanov, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49243 ) Change subject: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68b32730293fc83b5088074f71fa215220574748 Gerrit-Change-Number: 49243 Gerrit-PatchSet: 3 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 08 Jan 2021 19:20:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
by Srinidhi N Kaushik (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, John Zhao, Dossym Nurmukhanov, Raj Astekar, Patrick Rudolph. Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49243 ) Change subject: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68b32730293fc83b5088074f71fa215220574748 Gerrit-Change-Number: 49243 Gerrit-PatchSet: 3 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 08 Jan 2021 19:08:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Enable TC Cold support
by Srinidhi N Kaushik (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, John Zhao, Raj Astekar, Patrick Rudolph. Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Enable TC Cold support ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 08 Jan 2021 19:08:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
by Srinidhi N Kaushik (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Srinidhi N Kaushik, Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49243 to look at the new patch set (#3). Change subject: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers ...................................................................... vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers Update v 3444 FSP headers for Tiger Lake platform to include the below 2 UPDs to control TC cold support usb connect or not. FSPS: Usb3ComplModeEnable DisableTccoldOnUsbConnected BUG=b:173054070 TEST=Build and boot on delbin. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I68b32730293fc83b5088074f71fa215220574748 --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 1 file changed, 20 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/49243/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68b32730293fc83b5088074f71fa215220574748 Gerrit-Change-Number: 49243 Gerrit-PatchSet: 3 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
by Srinidhi N Kaushik (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49243 to look at the new patch set (#2). Change subject: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers ...................................................................... vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers Update v 3444 FSP headers for Tiger Lake platform to include the below 2 UPDs to control TC cold support usb connect or not. FSPS: Usb3ComplModeEnable DisableTccoldOnUsbConnected BUG=b:173054070 TEST=Build and boot on delbin. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I68b32730293fc83b5088074f71fa215220574748 --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 1 file changed, 20 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/49243/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68b32730293fc83b5088074f71fa215220574748 Gerrit-Change-Number: 49243 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/sconfig: Change __pci*|__pnp* device pointers to const
by Nico Huber (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Furquan Shaikh, Martin Roth. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49242 ) Change subject: util/sconfig: Change __pci*|__pnp* device pointers to const ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I061b05d994fc5c4156ee8bddabadf940f0aeeac3 Gerrit-Change-Number: 49242 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 18:32:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Enable TC Cold support
by Srinidhi N Kaushik (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Patrick Rudolph. Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Enable TC Cold support ...................................................................... soc/intel/tigerlake: Enable TC Cold support This change enables support for TC cold usb connect. BUG=b:173054070 TEST=Build and boot on delbin. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/49244/1 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 295f789..2a6a41c 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -134,6 +134,9 @@ */ params->ITbtConnectTopologyTimeoutInMs = 0; + /* Enable TcColdOnUsbConnect */ + params->DisableTccoldOnUsbConnected = 0; + /* Chipset Lockdown */ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { params->PchLockDownGlobalSmi = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
by Srinidhi N Kaushik (Code Review) 08 Jan '21

08 Jan '21

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49243 ) Change subject: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers ...................................................................... vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers Update v 3444 FSP headers for Tiger Lake platform to include the below 2 UPDs to control TC cold support usb connect or not. FSPS: Usb3ComplModeEnable DisableTccoldOnUsbConnected Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I68b32730293fc83b5088074f71fa215220574748 --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 1 file changed, 20 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/49243/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 276ac79..e791115 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -931,7 +931,17 @@ /** Offset 0x04BA - Reserved **/ - UINT8 Reserved20[7]; + UINT8 Reserved20[2]; + +/** Offset 0x04BC - Disable TC code On USB Connect + Enable(default) or Disable TC cold On Usb Connected + $EN_DIS +**/ + UINT8 DisableTccoldOnUsbConnected; + +/** Offset 0x04BD - Reserved +**/ + UINT8 Reserved21[4]; /** Offset 0x04C1 - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable @@ -965,7 +975,7 @@ /** Offset 0x04C6 - Reserved **/ - UINT8 Reserved21; + UINT8 Reserved22; /** Offset 0x04C7 - VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default) @@ -975,7 +985,7 @@ /** Offset 0x04C8 - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved23; /** Offset 0x04C9 - VMD Mem Bar1 Attributes 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH @@ -985,7 +995,7 @@ /** Offset 0x04CA - Reserved **/ - UINT8 Reserved23; + UINT8 Reserved24; /** Offset 0x04CB - VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH @@ -1001,7 +1011,7 @@ /** Offset 0x04CD - Reserved **/ - UINT8 Reserved24; + UINT8 Reserved25; /** Offset 0x04CE - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides @@ -1048,9 +1058,11 @@ **/ UINT8 VccSt; -/** Offset 0x04DD - Reserved +/** Offset 0x04DD - TCSS Usb3 Compliance Mode Enable + Used by IOM FW to skip powering down the PHY at the end of disconnect flow + $EN_DIS **/ - UINT8 Reserved25; + UINT8 Usb3ComplModeEnable; /** Offset 0x04DE - ITBT DMA LTR TCSS DMA1, DMA2 LTR value -- To view, visit https://review.coreboot.org/c/coreboot/+/49243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68b32730293fc83b5088074f71fa215220574748 Gerrit-Change-Number: 49243 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2021