Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49245 )
Change subject: soc/amd/cezzane: Add a minimal chipset tree ......................................................................
soc/amd/cezzane: Add a minimal chipset tree
This change adds a minimal chipset tree with only two devices: 1. Domain 2. GNB root complex
This allows sconfig to generate the config structure for SoC root device that is used by config_of_soc().
Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/chipset.cb 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/49245/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index cb613e3..4e0f4c8 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -25,6 +25,10 @@ select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
+config CHIPSET_DEVICETREE + string + default "soc/amd/cezanne/chipset.cb" + config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb new file mode 100644 index 0000000..49bd0c8 --- /dev/null +++ b/src/soc/amd/cezanne/chipset.cb @@ -0,0 +1,5 @@ +chip soc/amd/cezanne + device domain 0 on + device pci 00.0 alias gnb on end + end +end