coreboot-gerrit January 2021

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Change in coreboot[master]: soc/amd/picasso: add missing GNB I/O APIC initialization
by Felix Held (Code Review) 08 Jan '21

08 Jan '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48269 ) Change subject: soc/amd/picasso: add missing GNB I/O APIC initialization ...................................................................... soc/amd/picasso: add missing GNB I/O APIC initialization In order for this to really work, the GNB I/O APIC initialization part in FSP that enables the hardware unit and configures its base address need to be fixed too. Change-Id: Iddb0c20e769e6921ba5d0dd4a84ab9e494d522e1 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/root_complex.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/48269/1 diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 72a0974..f477a73 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpigen.h> +#include <arch/ioapic.h> #include <assert.h> #include <cbmem.h> #include <console/console.h> @@ -181,6 +182,11 @@ gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void root_complex_init(struct device *dev) +{ + setup_ioapic((u8 *)GNB_IO_APIC_ADDR, CONFIG_PICASSO_GNB_IOAPIC_ID); +} + static void dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size) { /* Name (buf_name, Buffer(size) {...} */ @@ -265,6 +271,7 @@ static struct device_operations root_complex_operations = { .read_resources = read_resources, .enable_resources = pci_dev_enable_resources, + .init = root_complex_init, .acpi_fill_ssdt = root_complex_fill_ssdt, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/48269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddb0c20e769e6921ba5d0dd4a84ab9e494d522e1 Gerrit-Change-Number: 48269 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: amd_blobs: Advance pointer for picasso FSP 0x25
by Felix Held (Code Review) 08 Jan '21

08 Jan '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49223 ) Change subject: amd_blobs: Advance pointer for picasso FSP 0x25 ...................................................................... amd_blobs: Advance pointer for picasso FSP 0x25 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I2aa5f353432cd8f79005153a06ac35c1e654f6f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49223 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 3e4a2e5..2fe8e5a 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 3e4a2e530f6f6dab7e9dc4af3feff9bdb2073b18 +Subproject commit 2fe8e5a1e0ae1c4b5939e5a5afa6fa69308491f8 -- To view, visit https://review.coreboot.org/c/coreboot/+/49223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aa5f353432cd8f79005153a06ac35c1e654f6f1 Gerrit-Change-Number: 49223 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Tim Crawford (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Nico Huber, Jeremy Soller, Angel Pons. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 6: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49104/comment/384f3082_6189bc00 PS5, Line 14: the TigerLake FSP Integration Guide. > I will clarify the it to be the table override behavior in the message, and reference the section in […] Done https://review.coreboot.org/c/coreboot/+/49104/comment/d990bb8c_16489ca9 PS5, Line 23: Tested by checking lspci output on System76 galp3-c, oryp5, oryp6. > These are WHL (galp3-c), CFL (oryp5, CB:47892), and CML (oryp6, CB:47768). […] Done File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/29a8388b_7c6d80c5 PS5, Line 552: 0 > No, what Nico means is that the resulting value of `segbusdevfuncregister` makes FSP try to rewrite […] Ack https://review.coreboot.org/c/coreboot/+/49104/comment/6ca257f9_c870f9ed PS5, Line 561: dev = pcidev_path_on_root(PCH_DEVFN_XHCI); : if (dev) : pci_dev_set_subsystem(dev, dev->subsystem_vendor, : dev->subsystem_device); : : dev = pcidev_path_on_root(PCH_DEVFN_HDA); : if (dev) : pci_dev_set_subsystem(dev, dev->subsystem_vendor, : dev->subsystem_device); > Yes. Based on your other comments, I believe this is the better option. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 15:13:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Tim Crawford (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Tim Crawford, Nico Huber, Jeremy Soller. Hello Felix Singer, build bot (Jenkins), Nico Huber, Jeremy Soller, Angel Pons, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49104 to look at the new patch set (#6). Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit Prevent the FSP from writing its default SVID SDID values of 8086:7270 for internal devices as this locks most of the registers. Allows the subsystemid values set in devicetree to be used. A description of this SSID table override behavior, along with example code, is provided in the TigerLake FSP Integration Guide, section 15.178 ("SI_CONFIG Struct Reference"). The xHCI and HDA devices have RW/L registers rather than RW/O registers. They can be written to multiple times but cannot be modified after being locked, which happens during FspSiliconInit. Because coreboot populates subsystem IDs after SiliconInit, these devices specifically must be written beforehand or will otherwise be locked with their default values of 0:0. Tested by checking lspci output on System76 galp3-c (WHL), oryp5 (CFL), and oryp6 (CML). References: - TigerLake FSP Integration Guide - Intel Document Number 337868-002 Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/49104/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/octopus: add audio codec into SSFC support for Bobba
by Marco Chen (Code Review) 08 Jan '21

08 Jan '21

Marco Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48795 ) Change subject: mb/google/octopus: add audio codec into SSFC support for Bobba ...................................................................... mb/google/octopus: add audio codec into SSFC support for Bobba BUG=b:174118027 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Signed-off-by: Marco Chen <marcochen(a)google.com> Change-Id: Id37c4c5716ade0851cfcb24e12b390841e633ac9 --- M src/mainboard/google/octopus/Kconfig.name M src/mainboard/google/octopus/variants/baseboard/Makefile.inc A src/mainboard/google/octopus/variants/baseboard/cbi_ssfc.c A src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h M src/mainboard/google/octopus/variants/baseboard/nhlt.c M src/mainboard/google/octopus/variants/bobba/overridetree.cb M src/mainboard/google/octopus/variants/bobba/variant.c 7 files changed, 134 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/48795/1 diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 6e3dbf4..76715a5 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -34,6 +34,7 @@ select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_MEEP bool "-> Meep" diff --git a/src/mainboard/google/octopus/variants/baseboard/Makefile.inc b/src/mainboard/google/octopus/variants/baseboard/Makefile.inc index 63b03a6..f28c3d6 100644 --- a/src/mainboard/google/octopus/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/octopus/variants/baseboard/Makefile.inc @@ -4,5 +4,6 @@ ramstage-y += gpio.c ramstage-y += nhlt.c +ramstage-y += cbi_ssfc.c smm-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/baseboard/cbi_ssfc.c b/src/mainboard/google/octopus/variants/baseboard/cbi_ssfc.c new file mode 100644 index 0000000..f8850ee --- /dev/null +++ b/src/mainboard/google/octopus/variants/baseboard/cbi_ssfc.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/cbi_ssfc.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> + +static int get_ssfc(uint32_t *val) +{ + static uint32_t known_value; + + if (known_value) { + *val = known_value; + return 0; + } + + if (google_chromeec_cbi_get_ssfc(&known_value) != 0) { + printk(BIOS_ERR, "SSFC not set in CBI\n"); + return -1; + } + + *val = known_value; + printk(BIOS_INFO, "SSFC 0x%x.\n", known_value); + + return 0; +} + +static unsigned int extract_field(uint32_t mask, int shift) +{ + uint32_t ssfc; + + /* On errors nothing is assumed to be set. */ + if (get_ssfc(&ssfc)) + return 0; + + return (ssfc >> shift) & mask; +} + +uint32_t ssfc_get_audio_codec(void) +{ + return extract_field(SSFC_AUDIO_CODEC_MASK, SSFC_AUDIO_CODEC_OFFSET); +} diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h new file mode 100644 index 0000000..a6b9cab --- /dev/null +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _OCTOPUS_CBI_SSFC__H_ +#define _OCTOPUS_CBI_SSFC__H_ + +#include <inttypes.h> + +/**************************************************************************** + * Octopus CBI Second Source Factory Cache + */ + +/* + * Audio Codec (Bits 9-11) + */ +enum ssfc_audio_codec { + SSFC_AUDIO_CODEC_DEFAULT, + SSFC_AUDIO_CODEC_DA7219, + SSFC_AUDIO_CODEC_RT5682, +}; +#define SSFC_AUDIO_CODEC_OFFSET 9 +#define SSFC_AUDIO_CODEC_MASK 0x7 + +uint32_t ssfc_get_audio_codec(void); + +#endif /* _OCTOPUS_CBI_SSFC__H_ */ diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c index f1304f4..1eab0c4 100644 --- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c +++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <baseboard/cbi_ssfc.h> #include <baseboard/variants.h> #include <console/console.h> #include <nhlt.h> @@ -7,6 +8,8 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) { + uint32_t codec = ssfc_get_audio_codec(); + /* 2 Channel DMIC array. */ if (!nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_ERR, "Added 2CH DMIC array.\n"); @@ -19,13 +22,13 @@ * Headset codec is bi-directional but uses the same configuration * settings for render and capture endpoints. */ - if (CONFIG(NHLT_DA7219)) { + if (CONFIG(NHLT_DA7219) && codec != SSFC_AUDIO_CODEC_RT5682) { /* Dialog for Headset codec */ if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2)) printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); } - if (CONFIG(NHLT_RT5682)) { + if (CONFIG(NHLT_RT5682) && codec == SSFC_AUDIO_CODEC_RT5682) { /* Realtek for Headset codec */ if (!nhlt_soc_add_rt5682(nhlt, AUDIO_LINK_SSP2)) printk(BIOS_ERR, "Added ALC5682 codec.\n"); diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 3c7187e..73adfef 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -165,6 +165,19 @@ register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "probed" = "1" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end end # - I2C 5 device pci 17.2 on chip drivers/i2c/generic diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index 2d09270..60c2796 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -4,10 +4,14 @@ #include <boardid.h> #include <sar.h> #include <baseboard/variants.h> -#include <delay.h> #include <gpio.h> #include <ec/google/chromeec/ec.h> #include <soc/intel/apollolake/chip.h> +#include <baseboard/cbi_ssfc.h> +#include <console/console.h> +#include <device/device.h> +#include <soc/pci_devs.h> +#include <string.h> enum { SKU_37_DROID = 37, /* LTE */ @@ -16,6 +20,47 @@ SKU_40_DROID = 40, /* LTE + Touch + KB backlight*/ }; +static void audio_codec_init_by_SSFC(void) +{ +#if !DEVTREE_EARLY + struct device *audio_i2c_host; + const struct device *audio_dev; + const struct bus *audio_i2c_bus; + char name; + + audio_i2c_host = pcidev_path_on_root(PCH_DEVFN_I2C5); + audio_i2c_bus = audio_i2c_host->link_list; + audio_dev = audio_i2c_bus->children; + + switch (ssfc_get_audio_codec()) { + case SSFC_AUDIO_CODEC_DEFAULT: + case SSFC_AUDIO_CODEC_DA7219: + name = 'D'; + printk(BIOS_INFO, "Enable DA7219.\n"); + break; + case SSFC_AUDIO_CODEC_RT5682: + name = 'R'; + printk(BIOS_ERR, "Enable RT5682.\n"); + break; + default: + printk(BIOS_ERR, + "can't identify any audio codec source from SSFC.\n"); + return; + } + + for (audio_dev = audio_dev; audio_dev; audio_dev = audio_dev->sibling) { + if (audio_dev->chip_ops && audio_dev->chip_ops->enable_dev) + audio_dev->chip_ops->enable_dev((struct device *)audio_dev); + printk(BIOS_ERR, "audio codec dev path %s.\n", dev_name((struct device *)audio_dev)); + + if (!strncmp(dev_name(audio_dev), &name, 1)) + ((struct device *)audio_dev)->enabled = 1; + else + ((struct device *)audio_dev)->enabled = 0; + } +#endif +} + const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; @@ -50,6 +95,8 @@ { struct soc_intel_apollolake_config *cfg = NULL; + audio_codec_init_by_SSFC(); + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; if (cfg != NULL && (cfg->disable_xhci_lfps_pm != 1)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/48795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id37c4c5716ade0851cfcb24e12b390841e633ac9 Gerrit-Change-Number: 48795 Gerrit-PatchSet: 1 Gerrit-Owner: Marco Chen <marcochen(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Angel Pons (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Tim Crawford, Nico Huber, Jeremy Soller. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/6ca82b65_81c5c2fb PS5, Line 552: 0 > You're right. The PCI ID database doesn't list anything using it, but it does appear to be valid. No, what Nico means is that the resulting value of `segbusdevfuncregister` makes FSP try to rewrite the PCI vendor/device ID register on the host bridge (PCI B:D.F 0:0.0), and it only works because said register is read-only. -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 13:10:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/external/tianocore/Kconfig: elaborate help for TIANOCORE_BOO...
by Felix Friedlander (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Martin Roth, Paul Menzel, Stefan Reinauer. Felix Friedlander has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49233 ) Change subject: payloads/external/tianocore/Kconfig: elaborate help for TIANOCORE_BOOTSPLASH_FILE ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49233/comment/1415b28f_c2b610f2 PS1, Line 7: payloads/external/tianocore/Kconfig: elaborate help for TIANOCORE_BOOTSPLASH_FILE > The prefix does not need to be the path (often it can be used though). Some suggestions: […] tianocore/Kconfig: Extend help for bootspash file Seem OK? File payloads/external/tianocore/Kconfig: https://review.coreboot.org/c/coreboot/+/49233/comment/ca503a1e_12c05175 PS1, Line 100: and will be displayed slightly above the centre of : the screen, > I do not understand this. […] From Microsoft's documentation on "boot screen components" (https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/boot-scre…): "We recommend that the logo is placed with its center at 38.2% from the screen's top edge." Someone on IRC seemed to be under the impression that the Coreboot TianoCore payload did exactly this, though I confess I haven't checked. https://review.coreboot.org/c/coreboot/+/49233/comment/c6124265_554d27b0 PS1, Line 102: than your display. > If you have it handy, it’d be great if you put the URL to the specification here too. Happy to - unfortunately, the actual ACPI specification is a PDF, so I can't hyperlink directly to the relevant part. Is "See section 5.2.22 of the ACPI specification: https://uefi.org/specifications" OK? -- To view, visit https://review.coreboot.org/c/coreboot/+/49233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4c6666bb0e49369fe8fe2ae3dc12c023f668da0 Gerrit-Change-Number: 49233 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Friedlander <felix(a)ffetc.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Jan 2021 13:02:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/emulation/qemu: Copy page tables to DRAM in assembly
by Arthur Heymans (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Martin Roth, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49228 ) Change subject: mb/emulation/qemu: Copy page tables to DRAM in assembly ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/emulation/qemu-i440fx/Kconfig: https://review.coreboot.org/c/coreboot/+/49228/comment/fd68b806_95bb51e1 PS1, Line 35: ARCH_X86_64_PGTBL_LOC Once you can migrate it to cbmem, could use the CAR symbols exposed with CONFIG_PAGING_IN_CACHE_AS_RAM and get rid of this? -- To view, visit https://review.coreboot.org/c/coreboot/+/49228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bdd2bef7197edd2e7488a8efdeba7eb4ab0dd4 Gerrit-Change-Number: 49228 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 12:33:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Sugnan Prabhu S (Code Review) 08 Jan '21

08 Jan '21

Sugnan Prabhu S has uploaded a new patch set (#72) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks, field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset, vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This will be used in the recovery scenario and also when booting with top-swap disabled i.e, RTC reset. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC (BUC) PCR register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If not, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top-swap is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE. Add documentation to describing the MCU update procedure. Update config name and Makefile.inc TODO: Since this update mechanism is dealing mostly with a single MCU it is best suited for systems where the CPU is soldered down and not replaceable (socketed). Extend the update mechanism to systems where the CPU is replaceable, by including multiple MCU for different CPUs. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sure that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/ucode_update/flash_layout.svg A Documentation/soc/intel/ucode_update/microcode_update_model.md M Makefile.inc A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c 7 files changed, 667 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/72 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 72 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/asurada: Implement HW reset function
by Yidi Lin (Code Review) 08 Jan '21

08 Jan '21

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49237 ) Change subject: mb/google/asurada: Implement HW reset function ...................................................................... mb/google/asurada: Implement HW reset function TEST=call do_board_reset() manually. Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I355f71e731f1045cd80a133cd31cf4d55f14d91f --- M src/mainboard/google/asurada/reset.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/49237/1 diff --git a/src/mainboard/google/asurada/reset.c b/src/mainboard/google/asurada/reset.c index 3a97ee5..91ee7c0 100644 --- a/src/mainboard/google/asurada/reset.c +++ b/src/mainboard/google/asurada/reset.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <gpio.h> #include <reset.h> +#include "gpio.h" + void do_board_reset(void) { + gpio_output(GPIO_RESET, 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I355f71e731f1045cd80a133cd31cf4d55f14d91f Gerrit-Change-Number: 49237 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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