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Change in coreboot[master]: [WIP] cpu/x86/smm: Use common APMC logging
by Kyösti Mälkki (Code Review) 08 Jan '21

08 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49248 ) Change subject: [WIP] cpu/x86/smm: Use common APMC logging ...................................................................... [WIP] cpu/x86/smm: Use common APMC logging Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/smm/Makefile.inc M src/cpu/x86/smm/smi_trigger.c M src/include/cpu/x86/smm.h M src/mainboard/dell/optiplex_9010/smihandler.c M src/mainboard/google/butterfly/smihandler.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/lenovo/s230u/smihandler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 15 files changed, 36 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/49248/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 1ed018d..9d74558 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -33,6 +33,7 @@ endif smm-y += save_state.c +smm-y += smi_trigger.c ifeq ($(CONFIG_SMM_TSEG),y) diff --git a/src/cpu/x86/smm/smi_trigger.c b/src/cpu/x86/smm/smi_trigger.c index 7e3ddb1..00d5371 100644 --- a/src/cpu/x86/smm/smi_trigger.c +++ b/src/cpu/x86/smm/smi_trigger.c @@ -4,24 +4,23 @@ #include <console/console.h> #include <cpu/x86/smm.h> -int apm_control(u8 cmd) +static void apmc_log(const char *fn, u8 cmd) { - if (!CONFIG(HAVE_SMI_HANDLER)) - return -1; - switch (cmd) { case APM_CNT_CST_CONTROL: + printk(BIOS_DEBUG, "%s: C-state control.\n", fn); break; case APM_CNT_PST_CONTROL: + printk(BIOS_DEBUG, "%s: P-state control.\n", fn); break; case APM_CNT_ACPI_DISABLE: - printk(BIOS_DEBUG, "Disabling ACPI via APMC.\n"); + printk(BIOS_DEBUG, "%s: Disabling ACPI.\n", fn); break; case APM_CNT_ACPI_ENABLE: - printk(BIOS_DEBUG, "Enabling ACPI via APMC.\n"); + printk(BIOS_DEBUG, "%s: Enabling ACPI.\n", fn); break; case APM_CNT_FINALIZE: - printk(BIOS_DEBUG, "Finalizing SMM.\n"); + printk(BIOS_DEBUG, "%s: Finalizing SMM.\n", fn); break; case APM_CNT_ELOG_GSMI: break; @@ -32,6 +31,15 @@ default: break; } +} + +int apm_control(u8 cmd) +{ + /* Never proceed inside SMI handler or without one. */ + if (ENV_SMM || !CONFIG(HAVE_SMI_HANDLER)) + return -1; + + apmc_log(__func__, cmd); /* Now raise the SMI. */ outb(cmd, APM_CNT); @@ -39,3 +47,12 @@ printk(BIOS_DEBUG, "APMC done.\n"); return 0; } + +u8 apm_get_apmc(void) +{ + /* Emulate B2 register as the FADT / Linux expects it */ + u8 cmd = inb(APM_CNT); + + apmc_log("SMI: ", cmd); + return cmd; +} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 9106842..31827cf 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -33,6 +33,7 @@ /* Send cmd to APM_CNT with HAVE_SMI_HANDLER checking. */ int apm_control(u8 cmd); +u8 apm_get_apmc(void); void io_trap_handler(int smif); int southbridge_io_trap_handler(int smif); diff --git a/src/mainboard/dell/optiplex_9010/smihandler.c b/src/mainboard/dell/optiplex_9010/smihandler.c index d3c83ef..f3ba57c 100644 --- a/src/mainboard/dell/optiplex_9010/smihandler.c +++ b/src/mainboard/dell/optiplex_9010/smihandler.c @@ -16,7 +16,6 @@ u8 val; switch (data) { case APM_CNT_ACPI_ENABLE: - printk(BIOS_SPEW, "%s: APM CNT EN: %02x\n", __func__, data); /* Enable wake on PS2 */ val = inb(SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_EN1); val |= (SCH5545_KBD_PME_EN | SCH5545_MOUSE_PME_EN); @@ -26,7 +25,6 @@ outb(SCH5545_GLOBAL_PME_EN, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_EN); break; case APM_CNT_ACPI_DISABLE: - printk(BIOS_SPEW, "%s: APM CNT DIS: %02x\n", __func__, data); /* Disable wake on PS2 */ val = inb(SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_EN1); val &= ~(SCH5545_KBD_PME_EN | SCH5545_MOUSE_PME_EN); diff --git a/src/mainboard/google/butterfly/smihandler.c b/src/mainboard/google/butterfly/smihandler.c index d71d9bf..0ffa0e6 100644 --- a/src/mainboard/google/butterfly/smihandler.c +++ b/src/mainboard/google/butterfly/smihandler.c @@ -36,16 +36,13 @@ int mainboard_smi_apmc(u8 apmc) { - printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc); switch (apmc) { case APM_CNT_ACPI_ENABLE: - printk(BIOS_DEBUG, "APMC: ACPI_EN\n"); /* Clear all pending events and enable SCI */ ec_write_cmd(EC_CMD_ENABLE_ACPI_MODE); break; case APM_CNT_ACPI_DISABLE: - printk(BIOS_DEBUG, "APMC: ACPI_DIS\n"); /* Clear all pending events and tell the EC that ACPI is disabled */ ec_write_cmd(EC_CMD_DISABLE_ACPI_MODE); break; diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 22e372d..89d4cac 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -67,10 +67,8 @@ int mainboard_smi_apmc(u8 apmc) { - printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc); switch (apmc) { case APM_CNT_ACPI_ENABLE: - printk(BIOS_DEBUG, "APMC: ACPI_EN\n"); /* Clear all pending events */ /* EC cmd:59 data:E8 */ ec_kbc_write_cmd(0x59); @@ -80,7 +78,6 @@ gpi_route_interrupt(EC_LID_GPI, GPI_IS_SCI); break; case APM_CNT_ACPI_DISABLE: - printk(BIOS_DEBUG, "APMC: ACPI_DIS\n"); /* Clear all pending events */ /* EC cmd:59 data:e9 */ ec_kbc_write_cmd(0x59); diff --git a/src/mainboard/lenovo/s230u/smihandler.c b/src/mainboard/lenovo/s230u/smihandler.c index 62bba44..f5fb9b4 100644 --- a/src/mainboard/lenovo/s230u/smihandler.c +++ b/src/mainboard/lenovo/s230u/smihandler.c @@ -74,18 +74,14 @@ int mainboard_smi_apmc(u8 data) { - printk(BIOS_INFO, "mainboard_smi_apmc(%02x)\n", data); - switch (data) { case APM_CNT_ACPI_ENABLE: - printk(BIOS_DEBUG, "Enable ACPI mode\n"); ec_enter_acpi_mode(); gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); gpi_route_interrupt(GPE_PALMDET1, GPI_IS_SCI); gpi_route_interrupt(GPE_PALMDET2, GPI_IS_SCI); break; case APM_CNT_ACPI_DISABLE: - printk(BIOS_DEBUG, "Disable ACPI mode\n"); ec_enter_apm_mode(); gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); break; diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 6fedba7..1a33444 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -281,9 +281,7 @@ { uint8_t reg8; - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); + reg8 = apm_get_apmc(); switch (reg8) { case APM_CNT_CST_CONTROL: /* @@ -291,7 +289,6 @@ * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "C-state control\n"); break; case APM_CNT_PST_CONTROL: /* @@ -299,15 +296,12 @@ * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: disable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: enable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index a4fdb01..7343d47 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -260,9 +260,7 @@ { uint8_t reg8; - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); + reg8 = apm_get_apmc(); switch (reg8) { case APM_CNT_CST_CONTROL: /* @@ -270,7 +268,6 @@ * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "C-state control\n"); break; case APM_CNT_PST_CONTROL: /* @@ -278,15 +275,12 @@ * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: disable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: enable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index 5ed52d8..02c795e 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -312,23 +312,17 @@ { u8 reg8; - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); + reg8 = apm_get_apmc(); switch (reg8) { case APM_CNT_CST_CONTROL: - printk(BIOS_DEBUG, "C-state control\n"); break; case APM_CNT_PST_CONTROL: - printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: disable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: enable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 51a3003..79605ce 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -331,9 +331,10 @@ { uint8_t reg8; - /* Emulate B2 register as the FADT / Linux expects it */ + reg8 = apm_get_apmc(); - reg8 = inb(APM_CNT); + apmc_log(__func__, reg8); + switch (reg8) { case APM_CNT_CST_CONTROL: /* @@ -341,7 +342,6 @@ * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "C-state control\n"); break; case APM_CNT_PST_CONTROL: /* @@ -349,15 +349,12 @@ * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: pmc_disable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: pmc_enable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index ae15795..f00d921 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -220,31 +220,25 @@ { uint8_t reg8; - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); + reg8 = apm_get_apmc(); switch (reg8) { case APM_CNT_CST_CONTROL: /* Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "C-state control\n"); break; case APM_CNT_PST_CONTROL: /* Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: disable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: enable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_FINALIZE: finalize(); diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index d59e29c..7256497 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -274,31 +274,25 @@ { u8 reg8; - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); + reg8 = apm_get_apmc(); switch (reg8) { case APM_CNT_CST_CONTROL: /* Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "C-state control\n"); break; case APM_CNT_PST_CONTROL: /* Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) & ~SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_FINALIZE: if (mainboard_finalized) { diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 19fe5bb..bb50eaa 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -297,35 +297,29 @@ u32 pmctrl; u8 reg8; - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); + reg8 = apm_get_apmc(); switch (reg8) { case APM_CNT_CST_CONTROL: /* Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "C-state control\n"); break; case APM_CNT_PST_CONTROL: /* Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: pmctrl = inl(pmbase + PM1_CNT); pmctrl &= ~SCI_EN; outl(pmctrl, pmbase + PM1_CNT); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: pmctrl = inl(pmbase + PM1_CNT); pmctrl |= SCI_EN; outl(pmctrl, pmbase + PM1_CNT); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; default: printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index bd44500..c923f68 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -262,9 +262,7 @@ u8 reg8; static int chipset_finalized = 0; - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); + reg8 = apm_get_apmc(); switch (reg8) { case APM_CNT_FINALIZE: if (chipset_finalized) { @@ -284,22 +282,18 @@ * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "C-state control\n"); break; case APM_CNT_PST_CONTROL: /* Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ - printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: disable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: enable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_ROUTE_ALL_XHCI: usb_xhci_route_all(); -- To view, visit https://review.coreboot.org/c/coreboot/+/49248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Gerrit-Change-Number: 49248 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: arch/x86: Use wildchar for mb/smihandler.c
by Kyösti Mälkki (Code Review) 08 Jan '21

08 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49247 ) Change subject: arch/x86: Use wildchar for mb/smihandler.c ...................................................................... arch/x86: Use wildchar for mb/smihandler.c Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Makefile.inc M src/mainboard/dell/optiplex_9010/Makefile.inc M src/mainboard/google/auron/Makefile.inc M src/mainboard/google/beltino/Makefile.inc M src/mainboard/google/brya/Makefile.inc M src/mainboard/google/butterfly/Makefile.inc R src/mainboard/google/butterfly/smihandler.c M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/dedede/Makefile.inc M src/mainboard/google/deltaur/Makefile.inc M src/mainboard/google/drallion/Makefile.inc M src/mainboard/google/eve/Makefile.inc M src/mainboard/google/fizz/Makefile.inc M src/mainboard/google/glados/Makefile.inc M src/mainboard/google/hatch/Makefile.inc M src/mainboard/google/jecht/Makefile.inc M src/mainboard/google/kahlee/Makefile.inc M src/mainboard/google/link/Makefile.inc R src/mainboard/google/link/smihandler.c M src/mainboard/google/octopus/Makefile.inc M src/mainboard/google/poppy/Makefile.inc M src/mainboard/google/rambi/Makefile.inc R src/mainboard/google/rambi/smihandler.c M src/mainboard/google/reef/Makefile.inc M src/mainboard/google/sarien/Makefile.inc M src/mainboard/google/slippy/Makefile.inc M src/mainboard/google/stout/Makefile.inc R src/mainboard/google/stout/smihandler.c M src/mainboard/google/volteer/Makefile.inc M src/mainboard/google/zork/Makefile.inc M src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc R src/mainboard/hp/pavilion_m6_1035dx/smihandler.c M src/mainboard/intel/adlrvp/Makefile.inc M src/mainboard/intel/baskingridge/Makefile.inc R src/mainboard/intel/baskingridge/smihandler.c M src/mainboard/intel/cannonlake_rvp/Makefile.inc M src/mainboard/intel/dcp847ske/Makefile.inc M src/mainboard/intel/glkrvp/Makefile.inc M src/mainboard/intel/jasperlake_rvp/Makefile.inc M src/mainboard/intel/kblrvp/Makefile.inc M src/mainboard/intel/kunimitsu/Makefile.inc M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/tglrvp/Makefile.inc M src/mainboard/lenovo/g505s/Makefile.inc R src/mainboard/lenovo/g505s/smihandler.c M src/mainboard/lenovo/l520/Makefile.inc M src/mainboard/lenovo/s230u/Makefile.inc M src/mainboard/lenovo/t410/Makefile.inc M src/mainboard/lenovo/t420/Makefile.inc M src/mainboard/lenovo/t420s/Makefile.inc M src/mainboard/lenovo/t430/Makefile.inc M src/mainboard/lenovo/t430s/Makefile.inc M src/mainboard/lenovo/t440p/Makefile.inc M src/mainboard/lenovo/t520/Makefile.inc M src/mainboard/lenovo/t530/Makefile.inc M src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc M src/mainboard/lenovo/x201/Makefile.inc M src/mainboard/lenovo/x220/Makefile.inc M src/mainboard/lenovo/x230/Makefile.inc M src/mainboard/packardbell/ms2290/Makefile.inc 60 files changed, 3 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/49247/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 2d3cda7..cfefec6 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -294,6 +294,4 @@ smm-y += memset.c smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c),) -smm-srcs += src/mainboard/$(MAINBOARDDIR)/smihandler.c -endif +smm-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c) diff --git a/src/mainboard/dell/optiplex_9010/Makefile.inc b/src/mainboard/dell/optiplex_9010/Makefile.inc index 7a8a684..964a7af 100644 --- a/src/mainboard/dell/optiplex_9010/Makefile.inc +++ b/src/mainboard/dell/optiplex_9010/Makefile.inc @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c - bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index 7d31655..006ac3d 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -6,8 +6,6 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c - romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 8c5d6c5..e12aa15 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -7,7 +7,7 @@ verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c ramstage-y += lan.c -smm-y += smihandler.c variants/$(VARIANT_DIR)/led.c +smm-y += variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index a186bfc..a7bc425 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -9,8 +9,6 @@ ramstage-y += mainboard.c ramstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c - VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) subdirs-y += variants/baseboard diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 342c9f7..33a97f5 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -7,8 +7,6 @@ bootblock-y += gpio.c romstage-y += gpio.c -smm-y += mainboard_smi.c - ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c romstage-y += early_init.c diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/smihandler.c similarity index 100% rename from src/mainboard/google/butterfly/mainboard_smi.c rename to src/mainboard/google/butterfly/smihandler.c diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 1ecc55e..4d10b66 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -10,8 +10,6 @@ ramstage-y += irqroute.c ramstage-y += w25q64.c -smm-y += smihandler.c - subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc index cd73bb0..1b5503d 100644 --- a/src/mainboard/google/dedede/Makefile.inc +++ b/src/mainboard/google/dedede/Makefile.inc @@ -10,8 +10,6 @@ ramstage-y += ec.c ramstage-y += board_info.c -smm-y += smihandler.c - VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) subdirs-y += variants/baseboard diff --git a/src/mainboard/google/deltaur/Makefile.inc b/src/mainboard/google/deltaur/Makefile.inc index 5881615..8adb584 100644 --- a/src/mainboard/google/deltaur/Makefile.inc +++ b/src/mainboard/google/deltaur/Makefile.inc @@ -16,8 +16,6 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += ec.c -smm-y += smihandler.c - subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc index 4c8b888..3c355c5 100644 --- a/src/mainboard/google/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/Makefile.inc @@ -6,8 +6,6 @@ romstage-y += romstage.c -smm-y += smihandler.c - bootblock-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc index ef8b0bd..fc6dc66 100644 --- a/src/mainboard/google/eve/Makefile.inc +++ b/src/mainboard/google/eve/Makefile.inc @@ -13,5 +13,3 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads - -smm-y += smihandler.c diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc index 13bf370..e192cff 100644 --- a/src/mainboard/google/fizz/Makefile.inc +++ b/src/mainboard/google/fizz/Makefile.inc @@ -13,8 +13,6 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-y += smihandler.c - subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc index 9bf6872..9fd41f8 100644 --- a/src/mainboard/google/glados/Makefile.inc +++ b/src/mainboard/google/glados/Makefile.inc @@ -15,8 +15,6 @@ ramstage-y += mainboard.c -smm-y += smihandler.c - ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index f82325f..debe942 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -12,7 +12,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 845fb0b..ed74d75 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -6,7 +6,7 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += lan.c -smm-y += smihandler.c led.c +smm-y += led.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index faa2496..9470592 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -16,8 +16,6 @@ verstage-y += chromeos.c verstage-y += ec.c -smm-y += smihandler.c - subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index ee411c2..6b3f1b5 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -6,8 +6,6 @@ ramstage-y += chromeos.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-y += mainboard_smi.c - # Order of names in SPD_SOURCES is important! SPD_SOURCES = elpida_4Gb_1600_x16 SPD_SOURCES += samsung_4Gb_1600_1.35v_x16 diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/smihandler.c similarity index 100% rename from src/mainboard/google/link/mainboard_smi.c rename to src/mainboard/google/link/smihandler.c diff --git a/src/mainboard/google/octopus/Makefile.inc b/src/mainboard/google/octopus/Makefile.inc index aa05524..1acd8c6 100644 --- a/src/mainboard/google/octopus/Makefile.inc +++ b/src/mainboard/google/octopus/Makefile.inc @@ -8,7 +8,6 @@ ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/poppy/Makefile.inc b/src/mainboard/google/poppy/Makefile.inc index 3b54531..9f36e79 100644 --- a/src/mainboard/google/poppy/Makefile.inc +++ b/src/mainboard/google/poppy/Makefile.inc @@ -13,7 +13,6 @@ ramstage-y += ramstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-y += smihandler.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c subdirs-y += variants/baseboard diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index da2e474..e0d5524 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -6,8 +6,6 @@ ramstage-y += irqroute.c ramstage-y += w25q64.c -smm-y += mainboard_smi.c - ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_BOARD_GOOGLE_NINJA) += variants/$(VARIANT_DIR)/lan.c diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/smihandler.c similarity index 100% rename from src/mainboard/google/rambi/mainboard_smi.c rename to src/mainboard/google/rambi/smihandler.c diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc index a115677..dd49610 100644 --- a/src/mainboard/google/reef/Makefile.inc +++ b/src/mainboard/google/reef/Makefile.inc @@ -8,7 +8,6 @@ ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index e7bfc53..e7c23b1 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -8,8 +8,6 @@ romstage-y += romstage.c -smm-y += smihandler.c - bootblock-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 8f75d72..2a2541d 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -5,8 +5,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c - romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index 5c196f0..a773a2d 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -5,7 +5,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -smm-y += mainboard_smi.c smm-y += ec.c SRC_ROOT = $(src)/mainboard/google/stout diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/smihandler.c similarity index 100% rename from src/mainboard/google/stout/mainboard_smi.c rename to src/mainboard/google/stout/smihandler.c diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc index c01f993..1847d56 100644 --- a/src/mainboard/google/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/Makefile.inc @@ -11,8 +11,6 @@ ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += mainboard.c -smm-y += smihandler.c - verstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc index 96c97b6..8a9d7af 100644 --- a/src/mainboard/google/zork/Makefile.inc +++ b/src/mainboard/google/zork/Makefile.inc @@ -11,8 +11,6 @@ verstage-y += verstage.c -smm-y += smihandler.c - subdirs-y += variants/baseboard subdirs-y += spd diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc index 77ae870..5d42eda 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc +++ b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc @@ -8,5 +8,3 @@ ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-y += ec.c - -smm-y += mainboard_smi.c diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c b/src/mainboard/hp/pavilion_m6_1035dx/smihandler.c similarity index 100% rename from src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c rename to src/mainboard/hp/pavilion_m6_1035dx/smihandler.c diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index de92406..75c8cf8 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -13,8 +13,6 @@ romstage-y += board_id.c romstage-y += memory.c -smm-y += smihandler.c - ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 46c9af2..9e60500 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -5,5 +5,3 @@ romstage-y += chromeos.c ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c - -smm-y += mainboard_smi.c diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/smihandler.c similarity index 100% rename from src/mainboard/intel/baskingridge/mainboard_smi.c rename to src/mainboard/intel/baskingridge/smihandler.c diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc index 695b1ff..9719015 100644 --- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc +++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc @@ -12,8 +12,6 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c - -smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index 28bc7c7..08aa2dd 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -3,4 +3,3 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-y += smihandler.c diff --git a/src/mainboard/intel/glkrvp/Makefile.inc b/src/mainboard/intel/glkrvp/Makefile.inc index ea5b2c6..37b60d0 100644 --- a/src/mainboard/intel/glkrvp/Makefile.inc +++ b/src/mainboard/intel/glkrvp/Makefile.inc @@ -10,7 +10,6 @@ ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/jasperlake_rvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/Makefile.inc index 2ac1b07..c680b23 100644 --- a/src/mainboard/intel/jasperlake_rvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/Makefile.inc @@ -15,8 +15,6 @@ ramstage-y += mainboard.c ramstage-y += board_id.c -smm-y += smihandler.c - subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/kblrvp/Makefile.inc b/src/mainboard/intel/kblrvp/Makefile.inc index c168b6d..80821eb 100644 --- a/src/mainboard/intel/kblrvp/Makefile.inc +++ b/src/mainboard/intel/kblrvp/Makefile.inc @@ -19,7 +19,5 @@ ramstage-y += hda_verb.c -smm-y += smihandler.c - subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index 63c39cf..f7ea681 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -13,5 +13,3 @@ ramstage-y += mainboard.c ramstage-y += ramstage.c - -smm-y += smihandler.c diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index bf35b66..21ae380 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -10,5 +10,3 @@ ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c - -smm-y += smihandler.c diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index 2ca32f3..93c9c49 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -11,8 +11,6 @@ romstage-y += romstage_fsp_params.c romstage-y += board_id.c -smm-y += smihandler.c - ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/lenovo/g505s/Makefile.inc b/src/mainboard/lenovo/g505s/Makefile.inc index 77ae870..5d42eda 100644 --- a/src/mainboard/lenovo/g505s/Makefile.inc +++ b/src/mainboard/lenovo/g505s/Makefile.inc @@ -8,5 +8,3 @@ ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-y += ec.c - -smm-y += mainboard_smi.c diff --git a/src/mainboard/lenovo/g505s/mainboard_smi.c b/src/mainboard/lenovo/g505s/smihandler.c similarity index 100% rename from src/mainboard/lenovo/g505s/mainboard_smi.c rename to src/mainboard/lenovo/g505s/smihandler.c diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 0126a75..e4b6fbf 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -2,7 +2,6 @@ bootblock-y += gpio.c romstage-y += gpio.c -smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index 12e7709..31bb642 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -1,7 +1,6 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += ec.c -smm-y += smihandler.c # FIXME: SPD images for samsung_8gb and hynix_8gb are missing. # It's possible that no mainboards with that variation were manufactured. diff --git a/src/mainboard/lenovo/t410/Makefile.inc b/src/mainboard/lenovo/t410/Makefile.inc index 20ec760..3b410c4 100644 --- a/src/mainboard/lenovo/t410/Makefile.inc +++ b/src/mainboard/lenovo/t410/Makefile.inc @@ -3,7 +3,6 @@ bootblock-y += early_init.c smm-y += dock.c -smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads romstage-y += dock.c diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 991eadb..e4b6fbf 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 991eadb..e4b6fbf 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index 0f49600..e402ffa 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -1,6 +1,5 @@ bootblock-y += gpio.c romstage-y += gpio.c -smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index 196a098..43a2a92 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/t440p/Makefile.inc b/src/mainboard/lenovo/t440p/Makefile.inc index fa6e7af..ebe01ae 100644 --- a/src/mainboard/lenovo/t440p/Makefile.inc +++ b/src/mainboard/lenovo/t440p/Makefile.inc @@ -1,3 +1,2 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index ab5aa4d..a3b838b 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index ab5aa4d..a3b838b 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index e9e74dd..ea3bd28 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -2,7 +2,6 @@ subdirs-y += spd -smm-y += smihandler.c bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc index 80e513c..d185f5c 100644 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ b/src/mainboard/lenovo/x201/Makefile.inc @@ -3,7 +3,6 @@ bootblock-y += early_init.c smm-y += dock.c -smm-y += smihandler.c romstage-y += dock.c ramstage-y += dock.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index d870c4d..b104bb5 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 5316d24..8e801f1 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += variants/$(VARIANT_DIR)/early_init.c bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/early_init.c diff --git a/src/mainboard/packardbell/ms2290/Makefile.inc b/src/mainboard/packardbell/ms2290/Makefile.inc index 9b1ea08..86b9433 100644 --- a/src/mainboard/packardbell/ms2290/Makefile.inc +++ b/src/mainboard/packardbell/ms2290/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -- To view, visit https://review.coreboot.org/c/coreboot/+/49247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481 Gerrit-Change-Number: 49247 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/tigerlake: Enable TC Cold support
by John Zhao (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Tim Wawrzynczak, John Zhao, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Enable TC Cold support ...................................................................... Patch Set 2: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 08 Jan 2021 22:19:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: vc/intel/FSP2_0/CPX-SP: update to FSP ww01 release
by Jonathan Zhang (Code Review) 08 Jan '21

08 Jan '21

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49246 ) Change subject: vc/intel/FSP2_0/CPX-SP: update to FSP ww01 release ...................................................................... vc/intel/FSP2_0/CPX-SP: update to FSP ww01 release With Intel CPX-SP FSP ww01 release, CidBitMap field is added to DimmDevice struct in hob_memmap.h. The copyright statements were updated to accomodate year 2021. gpio_fsp.h is not needed any more as coreboot takes over GPIO configuration. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I3242c8b50401757a28de8a9e9c71fb95bc0515dc --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h D src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h 10 files changed, 10 insertions(+), 214 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/49246/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h index 98a16d7..1ea5b07 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h @@ -2,7 +2,7 @@ Header file for Firmware Version Information @copyright - Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved. + Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h index 21b84a3..a42410c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h @@ -2,7 +2,7 @@ Intel FSP definition from Intel Firmware Support Package External Architecture Specification v2.0. - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved. + Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved. This file and the accompanying materials are licensed and made available under the terms and conditions of the BSD License. The full text of the license may be found at diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h index 7491aca..7a4373e 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index b4d4cad..8abff09 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h index fc08084..02e36ea 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h index b3c9661..e41d079 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h deleted file mode 100644 index be9d33f..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h +++ /dev/null @@ -1,205 +0,0 @@ -/** -Copyright (c) 2019-2020, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - - -#ifndef _GPIO_FSP_H_ -#define _GPIO_FSP_H_ - -// -// Below defines are based on GPIO_CONFIG structure fields -// -#define GPIO_CONF_PAD_MODE_MASK 0xF -#define GPIO_CONF_PAD_MODE_BIT_POS 0 -#define GPIO_CONF_HOST_OWN_MASK 0x3 -#define GPIO_CONF_HOST_OWN_BIT_POS 0 -#define GPIO_CONF_DIR_MASK 0x7 -#define GPIO_CONF_DIR_BIT_POS 0 -#define GPIO_CONF_INV_MASK 0x18 -#define GPIO_CONF_INV_BIT_POS 3 -#define GPIO_CONF_OUTPUT_MASK 0x3 -#define GPIO_CONF_OUTPUT_BIT_POS 0 -#define GPIO_CONF_INT_ROUTE_MASK 0x1F -#define GPIO_CONF_INT_ROUTE_BIT_POS 0 -#define GPIO_CONF_INT_TRIG_MASK 0xE0 -#define GPIO_CONF_INT_TRIG_BIT_POS 5 -#define GPIO_CONF_RESET_MASK 0x7 -#define GPIO_CONF_RESET_BIT_POS 0 -#define GPIO_CONF_TERM_MASK 0x1F -#define GPIO_CONF_TERM_BIT_POS 0 -#define GPIO_CONF_PADTOL_MASK 0x60 -#define GPIO_CONF_PADTOL_BIT_POS 5 -#define GPIO_CONF_LOCK_MASK 0x7 -#define GPIO_CONF_LOCK_BIT_POS 0 -#define GPIO_CONF_RXRAW_MASK 0x3 -#define GPIO_CONF_RXRAW_BIT_POS 0 - -typedef enum { GpioHardwareDefault = 0x0 } GPIO_HARDWARE_DEFAULT; - -/// -/// GPIO Pad Mode -/// -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7, - GpioPadModeNative4 = 0x9 -} GPIO_PAD_MODE; - -/// -/// Host Software Pad Ownership modes -/// -typedef enum { - GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified - GpioHostOwnAcpi = 0x1, ///< Set HOST ownership to ACPI - GpioHostOwnGpio = 0x3 ///< Set HOST ownership to GPIO -} GPIO_HOSTSW_OWN; - -/// -/// GPIO Direction -/// -typedef enum { - GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified - GpioDirInOut = - (0x1 | (0x1 << 3)), ///< Set pad for both output and input - GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and - ///input with inversion - GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only - GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion - GpioDirOut = 0x5, ///< Set pad for output only - GpioDirNone = 0x7 ///< Disable both output and input -} GPIO_DIRECTION; - -/// -/// GPIO Output State -/// -typedef enum { - GpioOutDefault = 0x0, ///< Leave output value unmodified - GpioOutLow = 0x1, ///< Set output to low - GpioOutHigh = 0x3 ///< Set output to high -} GPIO_OUTPUT_STATE; - -/// -/// GPIO interrupt configuration -/// This setting is applicable only if GPIO is in input mode. -/// GPIO_INT_CONFIG allows to choose which interrupt is generated -/// (IOxAPIC/SCI/SMI/NMI) -/// and how it is triggered (edge or level). -/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to -/// GpioIntBothEdgecan -/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel -/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad. -/// Not all GPIO are capable of generating an SMI or NMI interrupt -/// - -typedef enum { - GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified - GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation - GpioIntNmi = 0x3, ///< Enable NMI interrupt only - GpioIntSmi = 0x5, ///< Enable SMI interrupt only - GpioIntSci = 0x9, ///< Enable SCI interrupt only - GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only - GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered - GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of - ///edge depends on input inversion) - GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger - GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered -} GPIO_INT_CONFIG; - -/// -/// GPIO Power Configuration -/// GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified -/// Pad Register fields). -/// -typedef enum { - GpioResetDefault = 0x0, ///< Leave value of pad reset unmodified - GpioResetPwrGood = 0x1, ///< Powergood reset - GpioResetDeep = 0x3, ///< Deep GPIO Reset - GpioResetNormal = 0x5, ///< GPIO Reset - GpioResetResume = 0x7 ///< Resume Reset (applicable only for GPD group) -} GPIO_RESET_CONFIG; - -/// -/// GPIO Electrical Configuration -/// Set GPIO termination and Pad Tolerance (applicable only for some pads) -/// Field from GpioTermDefault to GpioTermNative can be OR'ed with -/// GpioTolerance1v8. -/// -typedef enum { - GpioTermDefault = 0x0, ///< Leave termination setting unmodified - GpioTermNone = 0x1, ///< none - GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down - GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down - GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up - GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up - GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up - GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up - GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up - GpioTermNative = 0x1F, ///< Native function controls pads termination - GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance - GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance -} GPIO_ELECTRICAL_CONFIG; - -/// -/// GPIO LockConfiguration -/// Set GPIO configuration lock and output state lock -/// GpioLockPadConfig and GpioLockOutputState can be OR'ed -/// -typedef enum { - GpioLockDefault = 0x0, ///< Leave lock setting unmodified - GpioPadConfigLock = 0x3, ///< Lock Pad Configuration - GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value -} GPIO_LOCK_CONFIG; - -/// -/// Other GPIO Configuration -/// GPIO_OTHER_CONFIG is used for less often settings and for future extensions -/// Supported settings: -/// - RX raw override to '1' - allows to override input value to '1' -/// This setting is applicable only if in input mode (both in GPIO and -/// native usage). -/// The override takes place at the internal pad state directly from buffer -/// and before the RXINV. -/// -typedef enum { - GpioRxRaw1Default = 0x0, ///< Use default input override value - GpioRxRaw1Dis = 0x1, ///< Don't override input - GpioRxRaw1En = 0x3 ///< Override input to '1' -} GPIO_OTHER_CONFIG; - -// -// Possible values of Pad Ownership -// -typedef enum { - GpioPadOwnHost = 0x0, - GpioPadOwnCsme = 0x1, - GpioPadOwnIsh = 0x2, -} GPIO_PAD_OWN; - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 9900a12..3c6f9a7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -1,5 +1,5 @@ /** -Copyright (c) 2019-2020, Intel Corporation. All rights reserved. +Copyright (c) 2019-2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 598d78c..52f3307 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -1,5 +1,5 @@ /** -Copyright (c) 2019-2020, Intel Corporation. All rights reserved. +Copyright (c) 2019-2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -127,6 +127,7 @@ UINT8 EnergyType; UINT8 reserved10[1]; UINT16 SPDRegVen; // Register Vendor ID in SPD + UINT8 CidBitMap; // SubRankPer CS for DIMM device } MEMMAP_DIMM_DEVICE_INFO_STRUCT; struct ChannelDevice { diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h index 9241692..93a1f9a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h @@ -1,5 +1,5 @@ /** -Copyright (c) 2019-2020, Intel Corporation. All rights reserved. +Copyright (c) 2019-2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: -- To view, visit https://review.coreboot.org/c/coreboot/+/49246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3242c8b50401757a28de8a9e9c71fb95bc0515dc Gerrit-Change-Number: 49246 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Configure Delbin USB2 ports for Type C
by John Zhao (Code Review) 08 Jan '21

08 Jan '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49202 ) Change subject: mb/google/volteer: Configure Delbin USB2 ports for Type C ...................................................................... mb/google/volteer: Configure Delbin USB2 ports for Type C Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU to recover a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Booted to kernel on Delbin board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/49202/1 diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 5774047..aa06d09 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -51,7 +51,9 @@ .tx_emp_enable = USB2_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_56P3MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + .type_c = 1, }" + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Acoustic settings register "AcousticNoiseMitigation" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/49202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f Gerrit-Change-Number: 49202 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: util/sconfig: Change __pci*|__pnp* device pointers to const
by Angel Pons (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Furquan Shaikh, Martin Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49242 ) Change subject: util/sconfig: Change __pci*|__pnp* device pointers to const ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I061b05d994fc5c4156ee8bddabadf940f0aeeac3 Gerrit-Change-Number: 49242 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 22:00:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asrock/h110m: Fix HECI state in devicetree
by Felix Singer (Code Review) 08 Jan '21

08 Jan '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49184 ) Change subject: mb/asrock/h110m: Fix HECI state in devicetree ...................................................................... mb/asrock/h110m: Fix HECI state in devicetree Disable HECI in devicetree making its state equal with the HeciEnabled option. Change-Id: I67a9f0a66bcc51c6153a76bfaaebdf1e7f07d55d Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/49184/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 909c050..ffa35f7 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -187,10 +187,8 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on # Management Engine Interface 1 + device pci 16.0 off # Management Engine Interface 1 subsystemid 0x1849 0xa131 - - # FIXME: does not match devicetree! register "HeciEnabled" = "0" end device pci 16.1 off end # Management Engine Interface 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67a9f0a66bcc51c6153a76bfaaebdf1e7f07d55d Gerrit-Change-Number: 49184 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Tim Crawford (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Nico Huber, Jeremy Soller, Angel Pons. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/43a5f0be_80fbfa12 PS6, Line 558: = {0} > Initialization is not required anymore. And actually never was, `static` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 21:32:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Tim Crawford (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Tim Crawford, Jeremy Soller, Angel Pons. Hello Felix Singer, build bot (Jenkins), Nico Huber, Jeremy Soller, Angel Pons, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49104 to look at the new patch set (#7). Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit Prevent the FSP from writing its default SVID SDID values of 8086:7270 for internal devices as this locks most of the registers. Allows the subsystemid values set in devicetree to be used. A description of this SSID table override behavior, along with example code, is provided in the TigerLake FSP Integration Guide, section 15.178 ("SI_CONFIG Struct Reference"). The xHCI and HDA devices have RW/L registers rather than RW/O registers. They can be written to multiple times but cannot be modified after being locked, which happens during FspSiliconInit. Because coreboot populates subsystem IDs after SiliconInit, these devices specifically must be written beforehand or will otherwise be locked with their default values of 0:0. Tested by checking lspci output on System76 galp3-c (WHL), oryp5 (CFL), and oryp6 (CML). References: - TigerLake FSP Integration Guide - Intel Document Number 337868-002 Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/49104/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/amdfwtool,post: add missing distclean target
by Felix Held (Code Review) 08 Jan '21

08 Jan '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49227 ) Change subject: util/amdfwtool,post: add missing distclean target ...................................................................... util/amdfwtool,post: add missing distclean target Without this target some spurious errors occurred when running make distclean at the top level of coreboot. Change-Id: I3d3061b386fc5b4a043cfc7ff8fd3c0da33c0e83 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49227 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/amdfwtool/Makefile M util/post/Makefile 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index 58606e3..c19c8e6 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -16,3 +16,5 @@ clean: @rm -f $(TARGET) $(OBJ) + +distclean: clean diff --git a/util/post/Makefile b/util/post/Makefile index d0a3eb9..0941cde 100644 --- a/util/post/Makefile +++ b/util/post/Makefile @@ -2,3 +2,5 @@ $(CC) post.c -o post clean: rm -f post + +distclean: clean -- To view, visit https://review.coreboot.org/c/coreboot/+/49227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d3061b386fc5b4a043cfc7ff8fd3c0da33c0e83 Gerrit-Change-Number: 49227 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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