coreboot-gerrit January 2021

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Change in coreboot[master]: mb/intel/adlrvp: Update GPIOs as per latest schematics
by Subrata Banik (Code Review) 09 Jan '21

09 Jan '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49260 ) Change subject: mb/intel/adlrvp: Update GPIOs as per latest schematics ...................................................................... mb/intel/adlrvp: Update GPIOs as per latest schematics 1. GPP_D8, GPP_H23 => Remove unused GPIOs 2. GPP_E18: GPP_E22 => Program the correct Native Functions for GPIO Change-Id: Iedb1f8fbf5f96a9617b72ba1a6419e3fd4e331b4 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/gpio.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/49260/1 diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 1943a66..0a6afcc 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -243,16 +243,17 @@ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D8, NONE), PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_NC(GPP_H23, NONE), /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2), PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), @@ -265,7 +266,6 @@ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), /* A21 : HDMI CRLS CTRLCLK */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/49260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedb1f8fbf5f96a9617b72ba1a6419e3fd4e331b4 Gerrit-Change-Number: 49260 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add new config for CPU PCIE ports
by Subrata Banik (Code Review) 09 Jan '21

09 Jan '21

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49259 ) Change subject: soc/intel/alderlake: Add new config for CPU PCIE ports ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > sure of course. […] Sure Eric, i will add u in review -- To view, visit https://review.coreboot.org/c/coreboot/+/49259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fd0ee8885a8b51df6b1692346d1a4fea3d66c8c Gerrit-Change-Number: 49259 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jan 2021 10:39:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add new config for CPU PCIE ports
by EricR Lai (Code Review) 09 Jan '21

09 Jan '21

EricR Lai has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49259 ) Change subject: soc/intel/alderlake: Add new config for CPU PCIE ports ...................................................................... Abandoned defer to Subrata -- To view, visit https://review.coreboot.org/c/coreboot/+/49259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fd0ee8885a8b51df6b1692346d1a4fea3d66c8c Gerrit-Change-Number: 49259 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/alderlake: Add new config for CPU PCIE ports
by EricR Lai (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49259 ) Change subject: soc/intel/alderlake: Add new config for CPU PCIE ports ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > do you mind if i use this submit this CL with all required change to enable CPU PCIE port. […] sure of course. Please let me know, cause it need it in the revise PCIE change :p -- To view, visit https://review.coreboot.org/c/coreboot/+/49259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fd0ee8885a8b51df6b1692346d1a4fea3d66c8c Gerrit-Change-Number: 49259 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 09 Jan 2021 10:37:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add new config for CPU PCIE ports
by Subrata Banik (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49259 ) Change subject: soc/intel/alderlake: Add new config for CPU PCIE ports ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: do you mind if i use this submit this CL with all required change to enable CPU PCIE port. Almost done with testing just about to submit the CL -- To view, visit https://review.coreboot.org/c/coreboot/+/49259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fd0ee8885a8b51df6b1692346d1a4fea3d66c8c Gerrit-Change-Number: 49259 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sat, 09 Jan 2021 10:33:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add new config for CPU PCIE ports
by EricR Lai (Code Review) 09 Jan '21

09 Jan '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49259 ) Change subject: soc/intel/alderlake: Add new config for CPU PCIE ports ...................................................................... soc/intel/alderlake: Add new config for CPU PCIE ports By ADL EDS, ADL has 3 CPU PCIE ports. RP1: 0/6/0 RP2: 0/1/0 RP3: 0/6/2 Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I1fd0ee8885a8b51df6b1692346d1a4fea3d66c8c --- M 3rdparty/libgfxinit M src/soc/intel/alderlake/Kconfig 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/49259/1 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index bc0588e..3318bf2 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit bc0588e482b1320d5739900b00a45033f5b587f4 +Subproject commit 3318bf26803c77d41b18bef6d7ae4e051b97f9f2 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index c73df50..7eda7a8 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -123,6 +123,10 @@ int default 12 +config MAX_CPU_PORTS + int + default 3 + config MAX_PCIE_CLOCKS int default 12 -- To view, visit https://review.coreboot.org/c/coreboot/+/49259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fd0ee8885a8b51df6b1692346d1a4fea3d66c8c Gerrit-Change-Number: 49259 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Angel Pons (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Tim Crawford, Nico Huber, Jeremy Soller. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 8: (2 comments) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/4f6239a2_db0ba898 PS7, Line 540: reserved1 > Done. I've left it unaligned, since it looks like only AGESA code does that. I use bitfields on sandybridge and keep the numbers aligned, but Jenkins complains about the spacing around colons. In any case, not a big deal. https://review.coreboot.org/c/coreboot/+/49104/comment/e305e39b_483c50c8 PS7, Line 582: params->SiNumberOfSsidTableEntry = i; > > and if the devices are disabled, the entries shouldn't hurt. […] Yeah, Nico's approach would be rather good. To avoid some redundancy, I'd use an array with the xHCI and HDA devfn's and a loop: const pci_devfn_t devfn_table[] = { PCH_DEVFN_XHCI, PCH_DEVFN_HDA }; static struct svid_ssid_init_entry ssid_table[ARRAY_SIZE(devfn_table)]; for (i = 0; i < ARRAY_SIZE(devfn_table); i++) { ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID; ssid_table[i].device = PCI_SLOT(devfn_table[i]); ssid_table[i].function = PCI_FUNC(devfn_table[i]); dev = pcidev_path_on_root(devfn_table[i]); if (dev) { ssid_table[i].svid = dev->subsystem_vendor; ssid_table[i].ssid = dev->subsystem_device; } } params->SiSsidTablePtr = (uintptr_t)ssid_table; params->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table); -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 8 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Sat, 09 Jan 2021 10:26:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb,soc/intel: Refactor power_on_after_fail option
by Kyösti Mälkki (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49251 to look at the new patch set (#4). Change subject: sb,soc/intel: Refactor power_on_after_fail option ...................................................................... sb,soc/intel: Refactor power_on_after_fail option It's only necessary to call get_option() with SLP_TYP S5. Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/pch/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 3 files changed, 37 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/49251/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/49251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce Gerrit-Change-Number: 49251 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: This change implements CrashLog for intel TGL.
by Francois Toguo Fotso (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Lance Zhao, Francois Toguo Fotso, Martin Roth, Patrick Rudolph. Hello Lance Zhao, build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49258 to look at the new patch set (#2). Change subject: This change implements CrashLog for intel TGL. ...................................................................... This change implements CrashLog for intel TGL. CrashLog is an diagnostic feature for Intel based platforms. It is meant to capture the state of the platform before a crash. The captured state of registers is preserve across a reset. Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> Change-Id: I2a4422ca5a61e2dac71cf46ca22ed793891ef85a [ Use bert_storage api for storing crashlog ] Signed-off-by: Nikunj A. Dadhania <nikunj.dadhania(a)intel.com> --- M src/acpi/acpi.c M src/commonlib/include/commonlib/cbmem_id.h M src/include/acpi/acpi.h M src/include/cper.h M src/soc/intel/common/Makefile.inc A src/soc/intel/common/acpi_bert_storage.c A src/soc/intel/common/block/include/intelblocks/bert_storage.h M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/chipset.cb A src/soc/intel/tigerlake/crashlog_lib.c A src/soc/intel/tigerlake/include/soc/crashlog_def.h A src/soc/intel/tigerlake/include/soc/crashlog_lib.h M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/romstage/fsp_params.c M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h 20 files changed, 1,605 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/49258/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a4422ca5a61e2dac71cf46ca22ed793891ef85a Gerrit-Change-Number: 49258 Gerrit-PatchSet: 2 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb,soc/intel: Refactor power_on_after_fail option
by Kyösti Mälkki (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49251 to look at the new patch set (#3). Change subject: sb,soc/intel: Refactor power_on_after_fail option ...................................................................... sb,soc/intel: Refactor power_on_after_fail option It's only necessary to call get_option() with SLP_TYP S5. Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/pch/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 3 files changed, 37 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/49251/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce Gerrit-Change-Number: 49251 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2021