EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49259 )
Change subject: soc/intel/alderlake: Add new config for CPU PCIE ports ......................................................................
soc/intel/alderlake: Add new config for CPU PCIE ports
By ADL EDS, ADL has 3 CPU PCIE ports. RP1: 0/6/0 RP2: 0/1/0 RP3: 0/6/2
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I1fd0ee8885a8b51df6b1692346d1a4fea3d66c8c --- M 3rdparty/libgfxinit M src/soc/intel/alderlake/Kconfig 2 files changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/49259/1
diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index bc0588e..3318bf2 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit bc0588e482b1320d5739900b00a45033f5b587f4 +Subproject commit 3318bf26803c77d41b18bef6d7ae4e051b97f9f2 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index c73df50..7eda7a8 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -123,6 +123,10 @@ int default 12
+config MAX_CPU_PORTS + int + default 3 + config MAX_PCIE_CLOCKS int default 12