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Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49104/comment/d33300b4_d3434245
PS10, Line 7: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
> This is a bit too long. How about […]
FSP-S*
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Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49104/comment/2f4b5846_e306a721
PS10, Line 7: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
This is a bit too long. How about
soc/intel/cnl: Allow setting PCIe subsystem IDs after FPS-S
?
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Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
......................................................................
Patch Set 10: Code-Review+2
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Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
......................................................................
Patch Set 10: Code-Review+2
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Jeremy Soller, Angel Pons, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49104
to look at the new patch set (#10).
Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
......................................................................
soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
Prevent the FSP from writing its default SVID SDID values of 8086:7270
for internal devices as this locks most of the registers. Allows the
subsystemid values set in devicetree to be used.
A description of this SSID table override behavior, along with example
code, is provided in the TigerLake FSP Integration Guide, section
15.178 ("SI_CONFIG Struct Reference").
The xHCI and HDA devices have RW/L registers rather than RW/O registers.
They can be written to multiple times but cannot be modified after
being locked, which happens during FspSiliconInit. Because coreboot
populates subsystem IDs after SiliconInit, these devices specifically
must be written beforehand or will otherwise be locked with their
default values of 0:0.
Tested by checking lspci output on System76 galp3-c (WHL), oryp5 (CFL),
and oryp6 (CML).
References:
- TigerLake FSP Integration Guide
- Intel Document Number 337868-002
Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e
Signed-off-by: Jeremy Soller <jeremy(a)system76.com>
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/49104/10
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Jeremy Soller, Angel Pons, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49104
to look at the new patch set (#9).
Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
......................................................................
soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
Prevent the FSP from writing its default SVID SDID values of 8086:7270
for internal devices as this locks most of the registers. Allows the
subsystemid values set in devicetree to be used.
A description of this SSID table override behavior, along with example
code, is provided in the TigerLake FSP Integration Guide, section
15.178 ("SI_CONFIG Struct Reference").
The xHCI and HDA devices have RW/L registers rather than RW/O registers.
They can be written to multiple times but cannot be modified after
being locked, which happens during FspSiliconInit. Because coreboot
populates subsystem IDs after SiliconInit, these devices specifically
must be written beforehand or will otherwise be locked with their
default values of 0:0.
Tested by checking lspci output on System76 galp3-c (WHL), oryp5 (CFL),
and oryp6 (CML).
References:
- TigerLake FSP Integration Guide
- Intel Document Number 337868-002
Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e
Signed-off-by: Jeremy Soller <jeremy(a)system76.com>
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/49104/9
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