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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 )
Change subject: soc/intel/skylake/acpi: Add PEP table
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49140/comment/8fa8acf3_ae7584e1
PS3, Line 11:
> tested? if you can, would be great if you test windoze and linux
Hmm. Not sure what I want to see, but it's probably not "CPU did not enter SLP_S0!!! (S0ix cnt=0)." The system does reach PC10 (from /sys/kernel/debug/pmc_core/package_cstate_show).
While I can't see which PCH IPs could be safely disabled, the LAN and WLAN devices remain powered on (based on reading, before and after, /sys/kernel/debug/pmc_core/mphy_core_lanes_power_gating_status and matching with HSIO lane ownership bits in FIA PCRs).
While the board has the SLP_S0# pad disconnected, this is not strictly required for S0ix, right?
Patchset:
PS3:
> Patch Set 3:
>
> > Patch Set 3:
> >
> > > Patch Set 3: -Code-Review
> > >
> > > > Patch Set 3: Code-Review-1
> > > >
> > > > > Patch Set 3: Code-Review+2
> > > > >
> > > > > wait... did I really forget SKL? 😮
> > > >
> > > > It was using PMC, not LPIT. Is that a problem?
> > >
> > > No, vendor firmware for my Skylake board uses both devices as well. So this seems to be fine?
> >
> > No, I reworked that. PMC/LPID/LPIT was actually confusing. PEP(D) is the "right" (or more correct) device name for this, so I cleaned this up but obviously forgot to add it to SKL as well 😄
> >
> > LPIT is related but a (very) different table, though.
>
> Öh oh well, actually that PMC that you mean (src/soc/intel/skylake/acpi/pmc.asl) is the "real" PMC. The "pmc.asl" (iirc the name correctly) was implementing LPID/PEPD. That was what I cleaned up.
Right, I meant the 'real' PMC. Since other platforms weren't moving from (PCIe device) PMC to PEPD, but from LPID to PEPD, it seems fine that Skylake has both?
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49251 )
Change subject: sb,soc/intel: Refactor power_on_after_fail option
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> why is this in SMM at all? other platforms set the bits as part of the soc init code in ramstage.
Supposedly changing CMOS with nvramtool takes immediate effect this way and does not require reboot.
I should move the inline comments about this, though.
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Change subject: sb,soc/intel: Refactor power_on_after_fail option
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
why is this in SMM at all? other platforms set the bits as part of the soc init code in ramstage.
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Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49201 )
Change subject: mb/google/parrot: Put trailing statement in the next line
......................................................................
mb/google/parrot: Put trailing statement in the next line
Fixes a linter error.
Change-Id: I3f74f25cb2e3edcdd509abd86d80098241c05741
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/google/parrot/smihandler.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/49201/1
diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c
index 9d96473..c27e15e 100644
--- a/src/mainboard/google/parrot/smihandler.c
+++ b/src/mainboard/google/parrot/smihandler.c
@@ -39,7 +39,8 @@
printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts);
if (gpi_sts & (1 << EC_SMI_GPI)) {
/* Process all pending events from EC */
- while (mainboard_smi_ec() != EC_NO_EVENT);
+ while (mainboard_smi_ec() != EC_NO_EVENT)
+ ;
} else if (gpi_sts & (1 << EC_LID_GPI)) {
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Jeremy Soller, Angel Pons, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49104
to look at the new patch set (#11).
Change subject: soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S
......................................................................
soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S
Prevent the FSP from writing its default SVID SDID values of 8086:7270
for internal devices as this locks most of the registers. Allows the
subsystemid values set in devicetree to be used.
A description of this SSID table override behavior, along with example
code, is provided in the TigerLake FSP Integration Guide, section
15.178 ("SI_CONFIG Struct Reference").
The xHCI and HDA devices have RW/L registers rather than RW/O registers.
They can be written to multiple times but cannot be modified after
being locked, which happens during FspSiliconInit. Because coreboot
populates subsystem IDs after SiliconInit, these devices specifically
must be written beforehand or will otherwise be locked with their
default values of 0:0.
Tested by checking lspci output on System76 galp3-c (WHL), oryp5 (CFL),
and oryp6 (CML).
References:
- TigerLake FSP Integration Guide
- Intel Document Number 337868-002
Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e
Signed-off-by: Jeremy Soller <jeremy(a)system76.com>
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/49104/11
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