coreboot-gerrit January 2021

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Change in coreboot[master]: This change implements CrashLog for intel TGL.
by Lance Zhao (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Francois Toguo Fotso, Martin Roth, Nikunj Dadhania, Patrick Rudolph. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49258 ) Change subject: This change implements CrashLog for intel TGL. ...................................................................... Patch Set 5: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49258/comment/ca990207_1c3efd8c PS5, Line 9: Intel based platforms It is not supported on all Intel platform, please make more specific. https://review.coreboot.org/c/coreboot/+/49258/comment/646c5744_73afe11a PS5, Line 14: Built, crashLog data generated, extracted, processed, decoded sucessfully. Test had been done which platform need to mentioned, is that Tigerlake RVP platform? Patchset: PS5: At least please separated the commit into ACPI BERT table related,and how TGL implement the feature File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/49258/comment/9b8a5ae0_86fc47ee PS5, Line 1557: current += bert->header.length; We may need a current = acpi_align_current(current); after Current had been updated. File src/include/cper.h: https://review.coreboot.org/c/coreboot/+/49258/comment/fbeb1991_887a8b1f PS5, Line 384: __packed Packed needed here? -- To view, visit https://review.coreboot.org/c/coreboot/+/49258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a4422ca5a61e2dac71cf46ca22ed793891ef85a Gerrit-Change-Number: 49258 Gerrit-PatchSet: 5 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 07:45:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: This change implements CrashLog for intel TGL.
by Francois Toguo Fotso (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Martin Roth, Francois Toguo Fotso, Nikunj Dadhania, Patrick Rudolph. Francois Toguo Fotso has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49258 ) Change subject: This change implements CrashLog for intel TGL. ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/49258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a4422ca5a61e2dac71cf46ca22ed793891ef85a Gerrit-Change-Number: 49258 Gerrit-PatchSet: 5 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 01:00:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,soc/intel/common: add support for Intel Low Power Idle Table
by Tim Wawrzynczak (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Michael Niewöhner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49045 ) Change subject: acpi,soc/intel/common: add support for Intel Low Power Idle Table ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e Gerrit-Change-Number: 49045 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sat, 09 Jan 2021 22:53:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Benjamin Doron (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Michael Niewöhner. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 ) Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49140/comment/8fa8acf3_ae7584e1 PS3, Line 11: > tested? if you can, would be great if you test windoze and linux Hmm. Not sure what I want to see, but it's probably not "CPU did not enter SLP_S0!!! (S0ix cnt=0)." The system does reach PC10 (from /sys/kernel/debug/pmc_core/package_cstate_show). While I can't see which PCH IPs could be safely disabled, the LAN and WLAN devices remain powered on (based on reading, before and after, /sys/kernel/debug/pmc_core/mphy_core_lanes_power_gating_status and matching with HSIO lane ownership bits in FIA PCRs). While the board has the SLP_S0# pad disconnected, this is not strictly required for S0ix, right? Patchset: PS3: > Patch Set 3: > > > Patch Set 3: > > > > > Patch Set 3: -Code-Review > > > > > > > Patch Set 3: Code-Review-1 > > > > > > > > > Patch Set 3: Code-Review+2 > > > > > > > > > > wait... did I really forget SKL? 😮 > > > > > > > > It was using PMC, not LPIT. Is that a problem? > > > > > > No, vendor firmware for my Skylake board uses both devices as well. So this seems to be fine? > > > > No, I reworked that. PMC/LPID/LPIT was actually confusing. PEP(D) is the "right" (or more correct) device name for this, so I cleaned this up but obviously forgot to add it to SKL as well 😄 > > > > LPIT is related but a (very) different table, though. > > Öh oh well, actually that PMC that you mean (src/soc/intel/skylake/acpi/pmc.asl) is the "real" PMC. The "pmc.asl" (iirc the name correctly) was implementing LPID/PEPD. That was what I cleaned up. Right, I meant the 'real' PMC. Since other platforms weren't moving from (PCIe device) PMC to PEPD, but from LPID to PEPD, it seems fine that Skylake has both? -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sat, 09 Jan 2021 19:30:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/hp/pavilion_m6_1035dx: Replace leading spaces with tabs
by Felix Singer (Code Review) 09 Jan '21

09 Jan '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49195 ) Change subject: mb/hp/pavilion_m6_1035dx: Replace leading spaces with tabs ...................................................................... mb/hp/pavilion_m6_1035dx: Replace leading spaces with tabs Replace leading spaces with tabs so that linter doesn't complain. Also, remove an unneeded empty line. Change-Id: I5809c1ca13782393cb4c4051a7061186c1c144e4 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c 1 file changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/49195/1 diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c index 95f2c93..b6cdc86 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c @@ -183,15 +183,14 @@ * data from the table. Otherwise, it will use its default conservative settings */ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), + ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), + CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - - PSO_END + PSO_END }; void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -- To view, visit https://review.coreboot.org/c/coreboot/+/49195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5809c1ca13782393cb4c4051a7061186c1c144e4 Gerrit-Change-Number: 49195 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb,soc/intel: Refactor power_on_after_fail option
by Kyösti Mälkki (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49251 ) Change subject: sb,soc/intel: Refactor power_on_after_fail option ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > why is this in SMM at all? other platforms set the bits as part of the soc init code in ramstage. Supposedly changing CMOS with nvramtool takes immediate effect this way and does not require reboot. I should move the inline comments about this, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/49251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce Gerrit-Change-Number: 49251 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 09 Jan 2021 17:00:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: sb,soc/intel: Refactor power_on_after_fail option
by Patrick Rudolph (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49251 ) Change subject: sb,soc/intel: Refactor power_on_after_fail option ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: why is this in SMM at all? other platforms set the bits as part of the soc init code in ramstage. -- To view, visit https://review.coreboot.org/c/coreboot/+/49251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce Gerrit-Change-Number: 49251 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 09 Jan 2021 16:38:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/parrot: Put trailing statement in the next line
by Felix Singer (Code Review) 09 Jan '21

09 Jan '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49201 ) Change subject: mb/google/parrot: Put trailing statement in the next line ...................................................................... mb/google/parrot: Put trailing statement in the next line Fixes a linter error. Change-Id: I3f74f25cb2e3edcdd509abd86d80098241c05741 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/parrot/smihandler.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/49201/1 diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 9d96473..c27e15e 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -39,7 +39,8 @@ printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts); if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending events from EC */ - while (mainboard_smi_ec() != EC_NO_EVENT); + while (mainboard_smi_ec() != EC_NO_EVENT) + ; } else if (gpi_sts & (1 << EC_LID_GPI)) { printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/49201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f74f25cb2e3edcdd509abd86d80098241c05741 Gerrit-Change-Number: 49201 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Update GPIOs as per latest schematics
by EricR Lai (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49260 ) Change subject: mb/intel/adlrvp: Update GPIOs as per latest schematics ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedb1f8fbf5f96a9617b72ba1a6419e3fd4e331b4 Gerrit-Change-Number: 49260 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Sat, 09 Jan 2021 16:24:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S
by Tim Crawford (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Jeremy Soller. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49104/comment/764b9558_98b64025 PS10, Line 7: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit > FSP-S* Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 11 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Sat, 09 Jan 2021 16:09:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit January 2021