Attention is currently required from: Michael Niewöhner. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 )
Change subject: soc/intel/skylake/acpi: Add PEP table ......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49140/comment/8fa8acf3_ae7584e1 PS3, Line 11:
tested? if you can, would be great if you test windoze and linux
Hmm. Not sure what I want to see, but it's probably not "CPU did not enter SLP_S0!!! (S0ix cnt=0)." The system does reach PC10 (from /sys/kernel/debug/pmc_core/package_cstate_show).
While I can't see which PCH IPs could be safely disabled, the LAN and WLAN devices remain powered on (based on reading, before and after, /sys/kernel/debug/pmc_core/mphy_core_lanes_power_gating_status and matching with HSIO lane ownership bits in FIA PCRs).
While the board has the SLP_S0# pad disconnected, this is not strictly required for S0ix, right?
Patchset:
PS3:
Patch Set 3:
Patch Set 3:
Patch Set 3: -Code-Review
Patch Set 3: Code-Review-1
Patch Set 3: Code-Review+2
wait... did I really forget SKL? 😮
It was using PMC, not LPIT. Is that a problem?
No, vendor firmware for my Skylake board uses both devices as well. So this seems to be fine?
No, I reworked that. PMC/LPID/LPIT was actually confusing. PEP(D) is the "right" (or more correct) device name for this, so I cleaned this up but obviously forgot to add it to SKL as well 😄
LPIT is related but a (very) different table, though.
Öh oh well, actually that PMC that you mean (src/soc/intel/skylake/acpi/pmc.asl) is the "real" PMC. The "pmc.asl" (iirc the name correctly) was implementing LPID/PEPD. That was what I cleaned up.
Right, I meant the 'real' PMC. Since other platforms weren't moving from (PCIe device) PMC to PEPD, but from LPID to PEPD, it seems fine that Skylake has both?