coreboot-gerrit January 2021

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Change in coreboot[master]: sb/intel/bd82x6x: Use `PCH_LPC_DEV` macro
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49170 ) Change subject: sb/intel/bd82x6x: Use `PCH_LPC_DEV` macro ...................................................................... sb/intel/bd82x6x: Use `PCH_LPC_DEV` macro Change-Id: I681bb126546b5a7bda3f1bac05c345d2cf60b178 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/smihandler.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/49170/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index f82c5ee..916cc1a 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -70,7 +70,7 @@ { u16 gpiobase; - gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; + gpiobase = pci_read_config16(PCH_LPC_DEV, GPIOBASE) & 0xfffc; if (!gpiobase) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/49170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I681bb126546b5a7bda3f1bac05c345d2cf60b178 Gerrit-Change-Number: 49170 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] cpu/x86/smm: Use common APMC logging
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49248 ) Change subject: [WIP] cpu/x86/smm: Use common APMC logging ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Gerrit-Change-Number: 49248 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 15:39:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/ibexpeak: Drop Global NVS support
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Alexander Couzens, Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49280 ) Change subject: sb/intel/ibexpeak: Drop Global NVS support ...................................................................... sb/intel/ibexpeak: Drop Global NVS support Was copy-pasted from bd82x6x and no mainboard actually needs it. Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/mainboard/lenovo/t410/acpi_tables.c M src/mainboard/lenovo/t410/smihandler.c D src/mainboard/lenovo/x201/acpi_tables.c M src/mainboard/lenovo/x201/smihandler.c M src/mainboard/packardbell/ms2290/smihandler.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/acpi/globalnvs.asl M src/southbridge/intel/ibexpeak/lpc.c D src/southbridge/intel/ibexpeak/nvs.h M src/southbridge/intel/ibexpeak/smihandler.c 10 files changed, 12 insertions(+), 403 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/49280/1 diff --git a/src/mainboard/lenovo/t410/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c deleted file mode 100644 index 45ae4d3..0000000 --- a/src/mainboard/lenovo/t410/acpi_tables.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi_gnvs.h> -#include <southbridge/intel/ibexpeak/nvs.h> - -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - /* The lid is open by default */ - gnvs->lids = 1; - - /* Temperature at which OS will shutdown */ - gnvs->tcrt = 100; - /* Temperature at which OS will throttle CPU */ - gnvs->tpsv = 90; -} diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c index 08b5d2f..9a6124b 100644 --- a/src/mainboard/lenovo/t410/smihandler.c +++ b/src/mainboard/lenovo/t410/smihandler.c @@ -3,7 +3,6 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/common/pmutil.h> #include <northbridge/intel/ironlake/ironlake.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c deleted file mode 100644 index 45ae4d3..0000000 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi_gnvs.h> -#include <southbridge/intel/ibexpeak/nvs.h> - -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - /* The lid is open by default */ - gnvs->lids = 1; - - /* Temperature at which OS will shutdown */ - gnvs->tcrt = 100; - /* Temperature at which OS will throttle CPU */ - gnvs->tpsv = 90; -} diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 08b5d2f..9a6124b 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -3,7 +3,6 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/common/pmutil.h> #include <northbridge/intel/ironlake/ironlake.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index b7f9aa9..0f2ca42 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <device/pci_ops.h> -#include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/common/pmutil.h> #include <northbridge/intel/ironlake/ironlake.h> #include <ec/acpi/ec.h> diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index c54c7e4..e082dc9 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -8,6 +8,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_NO_GLOBAL_NVS_SUPPORT select AZALIA_PLUGIN_SUPPORT select IOAPIC select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl index a650a68..a7c4fc0 100644 --- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl +++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl @@ -3,223 +3,15 @@ /* Global Variables */ Name(\PICM, 0) // IOAPIC/8259 +Name(\LIDS, 1) +Name(\MPEN, 1) +Name(\SMIF, 1) +Name(\PPCM, 0) +Name(\XHCI, 0) +Name(\OSYS, 2002) -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x100) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - /* Thermal policy */ - Offset (0x11), - TLVL, 8, // 0x11 - Throttle Level Limit - FLVL, 8, // 0x12 - Current FAN Level - TCRT, 8, // 0x13 - Critical Threshold - TPSV, 8, // 0x14 - Passive Threshold - TMAX, 8, // 0x15 - CPU Tj_max - F0OF, 8, // 0x16 - FAN 0 OFF Threshold - F0ON, 8, // 0x17 - FAN 0 ON Threshold - F0PW, 8, // 0x18 - FAN 0 PWM value - F1OF, 8, // 0x19 - FAN 1 OFF Threshold - F1ON, 8, // 0x1a - FAN 1 ON Threshold - F1PW, 8, // 0x1b - FAN 1 PWM value - F2OF, 8, // 0x1c - FAN 2 OFF Threshold - F2ON, 8, // 0x1d - FAN 2 ON Threshold - F2PW, 8, // 0x1e - FAN 2 PWM value - F3OF, 8, // 0x1f - FAN 3 OFF Threshold - F3ON, 8, // 0x20 - FAN 3 ON Threshold - F3PW, 8, // 0x21 - FAN 3 PWM value - F4OF, 8, // 0x22 - FAN 4 OFF Threshold - F4ON, 8, // 0x23 - FAN 4 ON Threshold - F4PW, 8, // 0x24 - FAN 4 PWM value - TMPS, 8, // 0x25 - Temperature Sensor ID - /* Processor Identification */ - Offset (0x28), - APIC, 8, // 0x28 - APIC Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable - PCP0, 8, // 0x2a - PDC CPU/CORE 0 - PCP1, 8, // 0x2b - PDC CPU/CORE 1 - PPCM, 8, // 0x2c - Max. PPC state - PCNT, 8, // 0x2d - Processor count - /* Super I/O & CMOS config */ - Offset (0x32), - NATP, 8, // 0x32 - - S5U0, 8, // 0x33 - Enable USB0 in S5 - S5U1, 8, // 0x34 - Enable USB1 in S5 - S3U0, 8, // 0x35 - Enable USB0 in S3 - S3U1, 8, // 0x36 - Enable USB1 in S3 - S33G, 8, // 0x37 - Enable 3G in S3 - CMEM, 32, // 0x38 - CBMEM TOC - /* Integrated Graphics Device */ - Offset (0x3c), - IGDS, 8, // 0x3c - IGD state (primary = 1) - TLST, 8, // 0x3d - Display Toggle List pointer - CADL, 8, // 0x3e - Currently Attached Devices List - PADL, 8, // 0x3f - Previously Attached Devices List - /* Backlight Control */ - Offset (0x64), - BLCS, 8, // 0x64 - Backlight control possible? - BRTL, 8, // 0x65 - Brightness Level - ODDS, 8, // 0x66 - /* Ambient Light Sensors */ - Offset (0x6e), - ALSE, 8, // 0x6e - ALS enable - ALAF, 8, // 0x6f - Ambient light adjustment factor - LLOW, 8, // 0x70 - LUX Low - LHIH, 8, // 0x71 - LUX High - /* EMA */ - Offset (0x78), - EMAE, 8, // 0x78 - EMA enable - EMAP, 16, // 0x79 - EMA pointer - EMAL, 16, // 0x7b - EMA length - /* MEF */ - Offset (0x82), - MEFE, 8, // 0x82 - MEF enable - /* TPM support */ - Offset (0x8c), - TPMP, 8, // 0x8c - TPM - TPME, 8, // 0x8d - TPM enable - /* SATA */ - Offset (0x96), - GTF0, 56, // 0x96 - GTF task file buffer for port 0 - GTF1, 56, // 0x9d - GTF task file buffer for port 1 - GTF2, 56, // 0xa4 - GTF task file buffer for port 2 - IDEM, 8, // 0xab - IDE mode (compatible / enhanced) - IDET, 8, // 0xac - IDE - /* XHCI */ - Offset (0xb2), - XHCI, 8, -} - -/* Set flag to enable USB charging in S3 */ -Method (S3UE) -{ - Store (One, \S3U0) - Store (One, \S3U1) -} - -/* Set flag to disable USB charging in S3 */ -Method (S3UD) -{ - Store (Zero, \S3U0) - Store (Zero, \S3U1) -} - -/* Set flag to enable USB charging in S5 */ -Method (S5UE) -{ - Store (One, \S5U0) - Store (One, \S5U1) -} - -/* Set flag to disable USB charging in S5 */ -Method (S5UD) -{ - Store (Zero, \S5U0) - Store (Zero, \S5U1) -} - -/* Set flag to enable 3G module in S3 */ -Method (S3GE) -{ - Store (One, \S33G) -} - -/* Set flag to disable 3G module in S3 */ -Method (S3GD) -{ - Store (Zero, \S33G) -} - -/* Set XHCI Mode enable */ -Method (XHCE) -{ - Store (One, \XHCI) -} - -/* Set XHCI Mode disable */ -Method (XHCD) -{ - Store (Zero, \XHCI) -} -External (\_TZ.SKIN) - -Method (TZUP) -{ -#ifdef HAVE_THERMALZONE - /* Update Primary Thermal Zone */ - If (CondRefOf (\_TZ.THRM)) { - Notify (\_TZ.THRM, 0x81) - } -#endif - - /* Update Secondary Thermal Zone */ - If (CondRefOf (\_TZ.SKIN)) { - Notify (\_TZ.SKIN, 0x81) - } -} - -/* Update Fan 0 thresholds */ -Method (F0UT, 2) -{ - Store (Arg0, \F0OF) - Store (Arg1, \F0ON) - TZUP () -} - -/* Update Fan 1 thresholds */ -Method (F1UT, 2) -{ - Store (Arg0, \F1OF) - Store (Arg1, \F1ON) - TZUP () -} - -/* Update Fan 2 thresholds */ -Method (F2UT, 2) -{ - Store (Arg0, \F2OF) - Store (Arg1, \F2ON) - TZUP () -} - -/* Update Fan 3 thresholds */ -Method (F3UT, 2) -{ - Store (Arg0, \F3OF) - Store (Arg1, \F3ON) - TZUP () -} - -/* Update Fan 4 thresholds */ -Method (F4UT, 2) -{ - Store (Arg0, \F4OF) - Store (Arg1, \F4ON) - TZUP () -} - -/* Update Temperature Sensor ID */ -Method (TMPU, 1) -{ - Store (Arg0, \TMPS) - TZUP () -} +/* Only H8 ACPI uses these */ +Name(\TCRT, 100) +Name(\TPSV, 90) +Name(\FLVL, 0) +Name(\PWRS, 0) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 3f59a19..40c9255 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -20,7 +20,6 @@ #include <cpu/x86/smm.h> #include "chip.h" #include "pch.h" -#include "nvs.h" #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/spi.h> @@ -541,30 +540,6 @@ pch_enable(dev); } -size_t gnvs_size_of_array(void) -{ - return sizeof(struct global_nvs); -} - -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); -} - -void southbridge_inject_dsdt(const struct device *dev) -{ - struct global_nvs *gnvs = acpi_get_gnvs(); - if (!gnvs) - return; - - soc_fill_gnvs(gnvs); - mainboard_fill_gnvs(gnvs); - - acpi_inject_nvsa(); -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; @@ -594,7 +569,6 @@ .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_inject_dsdt = southbridge_inject_dsdt, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .write_acpi_tables = acpi_write_hpet, diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h deleted file mode 100644 index 799af47..0000000 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H -#define SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H - -#include <commonlib/helpers.h> -#include <stdint.h> - -struct __packed global_nvs { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ - u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ - /* Thermal policy */ - u8 tlvl; /* 0x11 - Throttle Level Limit */ - u8 flvl; /* 0x12 - Current FAN Level */ - u8 tcrt; /* 0x13 - Critical Threshold */ - u8 tpsv; /* 0x14 - Passive Threshold */ - u8 tmax; /* 0x15 - CPU Tj_max */ - u8 f0of; /* 0x16 - FAN 0 OFF Threshold */ - u8 f0on; /* 0x17 - FAN 0 ON Threshold */ - u8 f0pw; /* 0x18 - FAN 0 PWM value */ - u8 f1of; /* 0x19 - FAN 1 OFF Threshold */ - u8 f1on; /* 0x1a - FAN 1 ON Threshold */ - u8 f1pw; /* 0x1b - FAN 1 PWM value */ - u8 f2of; /* 0x1c - FAN 2 OFF Threshold */ - u8 f2on; /* 0x1d - FAN 2 ON Threshold */ - u8 f2pw; /* 0x1e - FAN 2 PWM value */ - u8 f3of; /* 0x1f - FAN 3 OFF Threshold */ - u8 f3on; /* 0x20 - FAN 3 ON Threshold */ - u8 f3pw; /* 0x21 - FAN 3 PWM value */ - u8 f4of; /* 0x22 - FAN 4 OFF Threshold */ - u8 f4on; /* 0x23 - FAN 4 ON Threshold */ - u8 f4pw; /* 0x24 - FAN 4 PWM value */ - u8 tmps; /* 0x25 - Temperature Sensor ID */ - u8 rsvd3[2]; - /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ - u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ - u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ - u8 ppcm; /* 0x2c - Max. PPC state */ - u8 pcnt; /* 0x2d - Processor Count */ - u8 rsvd4[4]; - /* Super I/O & CMOS config */ - u8 natp; /* 0x32 - SIO type */ - u8 s5u0; /* 0x33 - Enable USB0 in S5 */ - u8 s5u1; /* 0x34 - Enable USB1 in S5 */ - u8 s3u0; /* 0x35 - Enable USB0 in S3 */ - u8 s3u1; /* 0x36 - Enable USB1 in S3 */ - u8 s33g; /* 0x37 - Enable S3 in 3G */ - u32 obsolete_cmem; /* 0x38 - CBMEM TOC */ - /* Integrated Graphics Device */ - u8 igds; /* 0x3c - IGD state */ - u8 tlst; /* 0x3d - Display Toggle List Pointer */ - u8 cadl; /* 0x3e - currently attached devices */ - u8 padl; /* 0x3f - previously attached devices */ - u8 rsvd5[36]; - /* Backlight Control */ - u8 blcs; /* 0x64 - Backlight Control possible */ - u8 brtl; - u8 odds; - u8 rsvd6[0x7]; - /* Ambient Light Sensors*/ - u8 alse; /* 0x6e - ALS enable */ - u8 alaf; - u8 llow; - u8 lhih; - u8 rsvd7[0x6]; - /* Extended Mobile Access */ - u8 emae; /* 0x78 - EMA enable */ - u16 emap; /* 0x79 - EMA pointer */ - u16 emal; /* 0x7a - EMA Length */ - u8 rsvd8[0x5]; - /* MEF */ - u8 mefe; /* 0x82 - MEF enable */ - u8 rsvd9[0x9]; - /* TPM support */ - u8 tpmp; /* 0x8c - TPM */ - u8 tpme; - u8 rsvd10[8]; - /* SATA */ - u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */ - u8 gtf1[7]; - u8 gtf2[7]; - u8 idem; - u8 idet; - u8 rsvd11[6]; - /* XHCI */ - u8 xhci; - u8 rsvd13[76]; /* 0xf5 - rsvd */ -}; - -#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */ diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e83a9de..7de2f36 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -13,8 +13,6 @@ #include <southbridge/intel/ibexpeak/me.h> #include "pch.h" -#include "nvs.h" - /* We are using PCIe accesses for now * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind @@ -23,23 +21,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmutil.h> -int southbridge_io_trap_handler(int smif) -{ - switch (smif) { - case 0x32: - printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: - * On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - */ - gnvs->smif = 0; - return 1; /* IO trap handled */ - } - - /* Not handled */ - return 0; -} - static void southbridge_gate_memory_reset_real(int offset, u16 use, u16 io, u16 lvl) { @@ -109,8 +90,6 @@ /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/49280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c Gerrit-Change-Number: 49280 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801jx: Drop Global NVS support
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49279 ) Change subject: sb/intel/i82801jx: Drop Global NVS support ...................................................................... sb/intel/i82801jx: Drop Global NVS support Was copy-pasted from i82801ix and no mainboard actually needs it. Change-Id: I400424540b52dc5d43aba15720b18ad57ea2ebda Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/acpi/platform.asl M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/lpc.c D src/southbridge/intel/i82801jx/nvs.h M src/southbridge/intel/i82801jx/smihandler.c 6 files changed, 7 insertions(+), 253 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/49279/1 diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index b1dda02..27dfe61 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -17,6 +17,7 @@ DBG0, 8 } +#if !CONFIG(ACPI_NO_GLOBAL_NVS_SUPPORT) /* SMI I/O Trap */ Method(TRAP, 1, Serialized) { @@ -24,6 +25,7 @@ TRP0 = 0 // Generate trap Return (SMIF) // Return value of SMI handler } +#endif /* ! ACPI_NO_GLOBAL_NVS_SUPPORT */ /* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 687cb45..fa1cb0b 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_NO_GLOBAL_NVS_SUPPORT select AZALIA_PLUGIN_SUPPORT select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 5c9e26e..98383e0 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -3,111 +3,5 @@ /* Global Variables */ Name(\PICM, 0) // IOAPIC/8259 - -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x100) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - DBGS, 8, // 0x11 - Debug State - LINX, 8, // 0x12 - Linux OS - DCKN, 8, // 0x13 - PCIe docking state - /* Thermal policy */ - Offset (0x14), - ACTT, 8, // 0x14 - active trip point - TPSV, 8, // 0x15 - passive trip point - TC1V, 8, // 0x16 - passive trip point TC1 - TC2V, 8, // 0x17 - passive trip point TC2 - TSPV, 8, // 0x18 - passive trip point TSP - TCRT, 8, // 0x19 - critical trip point - DTSE, 8, // 0x1a - Digital Thermal Sensor enable - DTS1, 8, // 0x1b - DT sensor 1 - FLVL, 8, // 0x1c - current fan level - /* Battery Support */ - Offset (0x1e), - BNUM, 8, // 0x1e - number of batteries - B0SC, 8, // 0x1f - BAT0 stored capacity - B1SC, 8, // 0x20 - BAT1 stored capacity - B2SC, 8, // 0x21 - BAT2 stored capacity - B0SS, 8, // 0x22 - BAT0 stored status - B1SS, 8, // 0x23 - BAT1 stored status - B2SS, 8, // 0x24 - BAT2 stored status - /* Processor Identification */ - Offset (0x28), - APIC, 8, // 0x28 - APIC Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable - PCP0, 8, // 0x2a - PDC CPU/CORE 0 - PCP1, 8, // 0x2b - PDC CPU/CORE 1 - PPCM, 8, // 0x2c - Max. PPC state - /* Super I/O & CMOS config */ - Offset (0x32), - NATP, 8, // 0x32 - - CMAP, 8, // 0x33 - - CMBP, 8, // 0x34 - - LPTP, 8, // 0x35 - LPT Port - FDCP, 8, // 0x36 - Floppy Disk Controller - RFDV, 8, // 0x37 - - HOTK, 8, // 0x38 - - RTCF, 8, // 0x39 - - UTIL, 8, // 0x3a - - ACIN, 8, // 0x3b - - /* Integrated Graphics Device */ - Offset (0x3c), - IGDS, 8, // 0x3c - IGD state (primary = 1) - TLST, 8, // 0x3d - Display Toggle List pointer - CADL, 8, // 0x3e - Currently Attached Devices List - PADL, 8, // 0x3f - Previously Attached Devices List - /* Backlight Control */ - Offset (0x64), - BLCS, 8, // 0x64 - Backlight control possible? - BRTL, 8, // 0x65 - Brightness Level - ODDS, 8, // 0x66 - /* Ambient Light Sensors */ - Offset (0x6e), - ALSE, 8, // 0x6e - ALS enable - ALAF, 8, // 0x6f - Ambient light adjustment factor - LLOW, 8, // 0x70 - LUX Low - LHIH, 8, // 0x71 - LUX High - /* EMA */ - Offset (0x78), - EMAE, 8, // 0x78 - EMA enable - EMAP, 16, // 0x79 - EMA pointer - EMAL, 16, // 0x7b - EMA length - /* MEF */ - Offset (0x82), - MEFE, 8, // 0x82 - MEF enable - /* TPM support */ - Offset (0x8c), - TPMP, 8, // 0x8c - TPM - TPME, 8, // 0x8d - TPM enable - /* SATA */ - Offset (0x96), - GTF0, 56, // 0x96 - GTF task file buffer for port 0 - GTF1, 56, // 0x9d - GTF task file buffer for port 1 - GTF2, 56, // 0xa4 - GTF task file buffer for port 2 - IDEM, 8, // 0xab - IDE mode (compatible / enhanced) - IDET, 8, // 0xac - IDE - /* Mainboard Specific (TODO move elsewhere) */ - Offset (0xf0), - DOCK, 8, // 0xf0 - Docking Status - BTEN, 8, // 0xf1 - Bluetooth Enable -} +Name(\MPEN, 1) +Name(\OSYS, 2002) diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 5c3a2df..796bd7a 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -19,7 +19,6 @@ #include <string.h> #include "chip.h" #include "i82801jx.h" -#include "nvs.h" #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/acpi_pirq_gen.h> @@ -476,26 +475,6 @@ } } -size_t gnvs_size_of_array(void) -{ - return sizeof(struct global_nvs); -} - -void southbridge_inject_dsdt(const struct device *dev) -{ - struct global_nvs *gnvs = acpi_get_gnvs(); - if (!gnvs) - return; - - gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ - - mainboard_fill_gnvs(gnvs); - acpi_inject_nvsa(); -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; @@ -514,7 +493,6 @@ .read_resources = i82801jx_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_inject_dsdt = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h deleted file mode 100644 index 48a7d87..0000000 --- a/src/southbridge/intel/i82801jx/nvs.h +++ /dev/null @@ -1,101 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOUTHBRIDGE_INTEL_I82801JX_NVS_H -#define SOUTHBRIDGE_INTEL_I82801JX_NVS_H -#include <stdint.h> - -struct __packed global_nvs { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ - u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ - u8 dbgs; /* 0x11 - Debug state */ - u8 linx; /* 0x12 - Linux OS */ - u8 dckn; /* 0x13 - PCIe docking state */ - /* Thermal policy */ - u8 actt; /* 0x14 - active trip point */ - u8 tpsv; /* 0x15 - passive trip point */ - u8 tc1v; /* 0x16 - passive trip point TC1 */ - u8 tc2v; /* 0x17 - passive trip point TC2 */ - u8 tspv; /* 0x18 - passive trip point TSP */ - u8 tcrt; /* 0x19 - critical trip point */ - u8 dtse; /* 0x1a - Digital Thermal Sensor enable */ - u8 dts1; /* 0x1b - DT sensor 1 */ - u8 flvl; /* 0x1c - current fan level */ - u8 rsvd2; - /* Battery Support */ - u8 bnum; /* 0x1e - number of batteries */ - u8 b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */ - u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ - u8 rsvd3[3]; - /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ - u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ - u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ - u8 ppcm; /* 0x2c - Max. PPC state */ - u8 rsvd4[5]; - /* Super I/O & CMOS config */ - u8 natp; /* 0x32 - SIO type */ - u8 cmap; /* 0x33 - */ - u8 cmbp; /* 0x34 - */ - u8 lptp; /* 0x35 - LPT port */ - u8 fdcp; /* 0x36 - Floppy Disk Controller */ - u8 rfdv; /* 0x37 - */ - u8 hotk; /* 0x38 - Hot Key */ - u8 rtcf; - u8 util; - u8 acin; - /* Integrated Graphics Device */ - u8 igds; /* 0x3c - IGD state */ - u8 tlst; /* 0x3d - Display Toggle List Pointer */ - u8 cadl; /* 0x3e - currently attached devices */ - u8 padl; /* 0x3f - previously attached devices */ - u8 rsvd5[36]; - /* Backlight Control */ - u8 blcs; /* 0x64 - Backlight Control possible */ - u8 brtl; - u8 odds; - u8 rsvd6[0x7]; - /* Ambient Light Sensors*/ - u8 alse; /* 0x6e - ALS enable */ - u8 alaf; - u8 llow; - u8 lhih; - u8 rsvd7[0x6]; - /* EMA */ - u8 emae; /* 0x78 - EMA enable */ - u16 emap; - u16 emal; - u8 rsvd8[0x5]; - /* MEF */ - u8 mefe; /* 0x82 - MEF enable */ - u8 rsvd9[0x9]; - /* TPM support */ - u8 tpmp; /* 0x8c - TPM */ - u8 tpme; - u8 rsvd10[8]; - /* SATA */ - u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */ - u8 gtf1[7]; - u8 gtf2[7]; - u8 idem; - u8 idet; - u8 rsvd11[67]; - /* Mainboard specific */ - u8 dock; /* 0xf0 - Docking Status */ - u8 bten; - u8 rsvd13[14]; -}; - -#endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 6a6c5b4..ed58a11 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -7,30 +7,11 @@ #include <southbridge/intel/common/pmutil.h> #include "i82801jx.h" -#include "nvs.h" - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -int southbridge_io_trap_handler(int smif) -{ - switch (smif) { - case 0x32: - printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: - * On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - */ - gnvs->smif = 0; - return 1; /* IO trap handled */ - } - - /* Not handled */ - return 0; -} - void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) @@ -47,10 +28,9 @@ mask |= (0xff << ((i - 16) << 3)); } - /* IOTRAP(3) SMI function call */ + /* IOTRAP(3) SMI function call (unused) */ if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif + printk(BIOS_DEBUG, "SMI function call not implemented\n"); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/49279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I400424540b52dc5d43aba15720b18ad57ea2ebda Gerrit-Change-Number: 49279 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: acpi: Add option to stub out Global NVS
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Lance Zhao, Martin Roth. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49278 ) Change subject: acpi: Add option to stub out Global NVS ...................................................................... acpi: Add option to stub out Global NVS Add the `ACPI_NO_GLOBAL_NVS_SUPPORT` Kconfig option. To be used in follow-ups that remove useless GNVS implementations from platforms. Change-Id: Ie31f02c9e279e47ff10562bb077367d4e33f4dd9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/acpi/Kconfig M src/acpi/Makefile.inc M src/acpi/gnvs.c A src/acpi/nvs_stub.c 4 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/49278/1 diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 293c194..9758d41 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -40,3 +40,8 @@ help This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. + +config ACPI_NO_GLOBAL_NVS_SUPPORT + bool + help + Selected by platforms that do not implement Global NVS. diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 1cd837d..b7ece61 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -13,6 +13,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos-gnvs.c ramstage-y += gnvs.c ramstage-$(CONFIG_ACPI_SOC_NVS) += nvs.c +ramstage-$(CONFIG_ACPI_NO_GLOBAL_NVS_SUPPORT) += nvs_stub.c ramstage-y += pld.c ramstage-y += sata.c ramstage-y += soundwire.c diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index c8478ee..0bcdba7 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -11,6 +11,9 @@ void *acpi_get_gnvs(void) { + if (CONFIG(ACPI_NO_GLOBAL_NVS_SUPPORT)) + return NULL; + if (gnvs) return gnvs; diff --git a/src/acpi/nvs_stub.c b/src/acpi/nvs_stub.c new file mode 100644 index 0000000..7abfb56 --- /dev/null +++ b/src/acpi/nvs_stub.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_gnvs.h> +#include <stddef.h> + +struct __packed global_nvs { +}; + +size_t gnvs_size_of_array(void) +{ + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/49278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie31f02c9e279e47ff10562bb077367d4e33f4dd9 Gerrit-Change-Number: 49278 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: i82801jx boards: Factor out GNVS initialisation
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49277 ) Change subject: i82801jx boards: Factor out GNVS initialisation ...................................................................... i82801jx boards: Factor out GNVS initialisation All boards use the same values. Change-Id: If473373bf093a438a80a58039472d288a28c41ef Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/mainboard/acer/g43t-am3/acpi_tables.c D src/mainboard/asus/p5qc/acpi_tables.c M src/mainboard/asus/p5ql-em/Makefile.inc D src/mainboard/asus/p5ql-em/acpi_tables.c A src/mainboard/asus/p5ql-em/cstates.c D src/mainboard/intel/dg43gt/acpi_tables.c M src/southbridge/intel/i82801jx/lpc.c 7 files changed, 16 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/49277/1 diff --git a/src/mainboard/acer/g43t-am3/acpi_tables.c b/src/mainboard/acer/g43t-am3/acpi_tables.c deleted file mode 100644 index 2bdb744..0000000 --- a/src/mainboard/acer/g43t-am3/acpi_tables.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi_gnvs.h> -#include <southbridge/intel/i82801jx/nvs.h> - -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ -} diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c deleted file mode 100644 index c9e4a5e..0000000 --- a/src/mainboard/asus/p5qc/acpi_tables.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi_gnvs.h> -#include <southbridge/intel/i82801jx/nvs.h> - -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ -} diff --git a/src/mainboard/asus/p5ql-em/Makefile.inc b/src/mainboard/asus/p5ql-em/Makefile.inc index 097c9f9..4a5e88d 100644 --- a/src/mainboard/asus/p5ql-em/Makefile.inc +++ b/src/mainboard/asus/p5ql-em/Makefile.inc @@ -5,4 +5,6 @@ romstage-y += gpio.c romstage-y += early_init.c +ramstage-y += cstates.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c deleted file mode 100644 index 37af4b5..0000000 --- a/src/mainboard/asus/p5ql-em/acpi_tables.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpigen.h> -#include <acpi/acpi_gnvs.h> -#include <southbridge/intel/i82801jx/nvs.h> - -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ -} - -/* TODO: Could work... */ -int get_cst_entries(acpi_cstate_t **entries) -{ - return 0; -} diff --git a/src/mainboard/asus/p5ql-em/cstates.c b/src/mainboard/asus/p5ql-em/cstates.c new file mode 100644 index 0000000..791f78e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cstates.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> + +/* TODO: Could work... */ +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/intel/dg43gt/acpi_tables.c b/src/mainboard/intel/dg43gt/acpi_tables.c deleted file mode 100644 index c9e4a5e..0000000 --- a/src/mainboard/intel/dg43gt/acpi_tables.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi_gnvs.h> -#include <southbridge/intel/i82801jx/nvs.h> - -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ -} diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 86478fa..5c3a2df 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -487,6 +487,11 @@ if (!gnvs) return; + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ + mainboard_fill_gnvs(gnvs); acpi_inject_nvsa(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If473373bf093a438a80a58039472d288a28c41ef Gerrit-Change-Number: 49277 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: i82801jx boards: Do not initialize unused `cmap`
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49276 ) Change subject: i82801jx boards: Do not initialize unused `cmap` ...................................................................... i82801jx boards: Do not initialize unused `cmap` Nothing uses the value of this field, so don't initialize it. Change-Id: Ic36f7d68f066719beb5f59bce2ada9671ce52072 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/p5qc/acpi_tables.c M src/mainboard/asus/p5ql-em/acpi_tables.c M src/mainboard/intel/dg43gt/acpi_tables.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/49276/1 diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c index 0d0b24c..c9e4a5e 100644 --- a/src/mainboard/asus/p5qc/acpi_tables.c +++ b/src/mainboard/asus/p5qc/acpi_tables.c @@ -9,5 +9,4 @@ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->apic = 1; /* Enable APIC */ gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c index e678bab..37af4b5 100644 --- a/src/mainboard/asus/p5ql-em/acpi_tables.c +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -10,7 +10,6 @@ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->apic = 1; /* Enable APIC */ gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } /* TODO: Could work... */ diff --git a/src/mainboard/intel/dg43gt/acpi_tables.c b/src/mainboard/intel/dg43gt/acpi_tables.c index 0d0b24c..c9e4a5e 100644 --- a/src/mainboard/intel/dg43gt/acpi_tables.c +++ b/src/mainboard/intel/dg43gt/acpi_tables.c @@ -9,5 +9,4 @@ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->apic = 1; /* Enable APIC */ gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/49276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic36f7d68f066719beb5f59bce2ada9671ce52072 Gerrit-Change-Number: 49276 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/foxconn,gigabyte: Drop GNVS lptp and fdcp
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Damien Zammit. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49275 ) Change subject: mb/foxconn,gigabyte: Drop GNVS lptp and fdcp ...................................................................... mb/foxconn,gigabyte: Drop GNVS lptp and fdcp Change-Id: Iaa05c1162b2533957091c719ea43ffb8d004c5eb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/foxconn/g41s-k/acpi_tables.c M src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c 2 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/49275/1 diff --git a/src/mainboard/foxconn/g41s-k/acpi_tables.c b/src/mainboard/foxconn/g41s-k/acpi_tables.c index e0a0749..7442804 100644 --- a/src/mainboard/foxconn/g41s-k/acpi_tables.c +++ b/src/mainboard/foxconn/g41s-k/acpi_tables.c @@ -6,6 +6,4 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->lptp = 0; /* LPT port */ - gnvs->fdcp = 0; /* Floppy Disk Controller */ } diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c index ca206b5..4d892c6 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c @@ -6,7 +6,5 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->lptp = 0; /* LPT port */ - gnvs->fdcp = 0; /* Floppy Disk Controller */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/49275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa05c1162b2533957091c719ea43ffb8d004c5eb Gerrit-Change-Number: 49275 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Attention: Damien Zammit Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mainboards: Drop GNVS cmap and cmbp
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Damien Zammit, Angel Pons, Evgeny Zinoviev, Alexander Couzens, Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49274 ) Change subject: mainboards: Drop GNVS cmap and cmbp ...................................................................... mainboards: Drop GNVS cmap and cmbp Functionality depends of CMAP and CMBP references inside board specific ASL implementation. Only roda/rk9 and roda/rk886ex has that. Change-Id: I4da8292375cb589d67dc68496b1e81971bc2a61f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- D src/mainboard/apple/macbook21/acpi_tables.c M src/mainboard/asrock/g41c-gs/acpi_tables.c M src/mainboard/asus/p5qc/acpi_tables.c M src/mainboard/asus/p5ql-em/acpi_tables.c M src/mainboard/asus/p5qpl-am/acpi_tables.c M src/mainboard/emulation/qemu-q35/acpi_tables.c M src/mainboard/foxconn/g41s-k/acpi_tables.c M src/mainboard/getac/p470/acpi_tables.c M src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c D src/mainboard/ibase/mb899/acpi_tables.c M src/mainboard/intel/dg41wv/acpi_tables.c M src/mainboard/intel/dg43gt/acpi_tables.c D src/mainboard/kontron/986lcd-m/acpi_tables.c M src/mainboard/lenovo/t400/acpi_tables.c M src/mainboard/lenovo/t60/acpi_tables.c M src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c M src/mainboard/lenovo/x200/acpi_tables.c M src/mainboard/lenovo/x60/acpi_tables.c 18 files changed, 0 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/49274/1 diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c deleted file mode 100644 index 6970dfc..0000000 --- a/src/mainboard/apple/macbook21/acpi_tables.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi_gnvs.h> -#include <southbridge/intel/i82801gx/nvs.h> - -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - -} diff --git a/src/mainboard/asrock/g41c-gs/acpi_tables.c b/src/mainboard/asrock/g41c-gs/acpi_tables.c index 720652663..d14f59e 100644 --- a/src/mainboard/asrock/g41c-gs/acpi_tables.c +++ b/src/mainboard/asrock/g41c-gs/acpi_tables.c @@ -6,5 +6,4 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c index 5063ae6..d519632 100644 --- a/src/mainboard/asus/p5qc/acpi_tables.c +++ b/src/mainboard/asus/p5qc/acpi_tables.c @@ -7,5 +7,4 @@ { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c index 21457ac..2094139 100644 --- a/src/mainboard/asus/p5ql-em/acpi_tables.c +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -8,7 +8,6 @@ { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } /* TODO: Could work... */ diff --git a/src/mainboard/asus/p5qpl-am/acpi_tables.c b/src/mainboard/asus/p5qpl-am/acpi_tables.c index 720652663..d14f59e 100644 --- a/src/mainboard/asus/p5qpl-am/acpi_tables.c +++ b/src/mainboard/asus/p5qpl-am/acpi_tables.c @@ -6,5 +6,4 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 15f2e56..d17f1d4 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -16,9 +16,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; } void mainboard_fill_fadt(acpi_fadt_t *fadt) diff --git a/src/mainboard/foxconn/g41s-k/acpi_tables.c b/src/mainboard/foxconn/g41s-k/acpi_tables.c index 38c0704..e0a0749 100644 --- a/src/mainboard/foxconn/g41s-k/acpi_tables.c +++ b/src/mainboard/foxconn/g41s-k/acpi_tables.c @@ -6,8 +6,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->cmap = 1; /* COM 1 port */ - gnvs->cmap = 1; /* COM 2 port */ gnvs->lptp = 0; /* LPT port */ gnvs->fdcp = 0; /* Floppy Disk Controller */ } diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 96e3d31..2de388a 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -3,19 +3,10 @@ #include <string.h> #include <console/console.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <device/device.h> -#include <southbridge/intel/i82801gx/nvs.h> #include "mainboard.h" -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - /* Enable COM port(s) */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x00; -} - static long acpi_create_ecdt(acpi_ecdt_t * ecdt) { /* Attention: Make sure these match the values from diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c index 3e06c96..ca206b5 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c @@ -9,5 +9,4 @@ gnvs->lptp = 0; /* LPT port */ gnvs->fdcp = 0; /* Floppy Disk Controller */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c deleted file mode 100644 index 6970dfc..0000000 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi_gnvs.h> -#include <southbridge/intel/i82801gx/nvs.h> - -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - -} diff --git a/src/mainboard/intel/dg41wv/acpi_tables.c b/src/mainboard/intel/dg41wv/acpi_tables.c index 720652663..d14f59e 100644 --- a/src/mainboard/intel/dg41wv/acpi_tables.c +++ b/src/mainboard/intel/dg41wv/acpi_tables.c @@ -6,5 +6,4 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/intel/dg43gt/acpi_tables.c b/src/mainboard/intel/dg43gt/acpi_tables.c index 5063ae6..d519632 100644 --- a/src/mainboard/intel/dg43gt/acpi_tables.c +++ b/src/mainboard/intel/dg43gt/acpi_tables.c @@ -7,5 +7,4 @@ { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c deleted file mode 100644 index 6970dfc..0000000 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi_gnvs.h> -#include <southbridge/intel/i82801gx/nvs.h> - -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - -} diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 9c9a951..f4f8040 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -9,11 +9,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - /* Temperature at which OS will shutdown */ gnvs->tcrt = 100; /* Temperature at which OS will throttle CPU */ diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 4a9c6ae..d742db0 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -5,10 +5,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - /* Temperature at which OS will shutdown */ gnvs->tcrt = 100; /* Temperature at which OS will throttle CPU */ diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c index 720652663..d14f59e 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c +++ b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c @@ -6,5 +6,4 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 9c9a951..f4f8040 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -9,11 +9,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - /* Temperature at which OS will shutdown */ gnvs->tcrt = 100; /* Temperature at which OS will throttle CPU */ diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 4a9c6ae..d742db0 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -5,10 +5,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - /* Temperature at which OS will shutdown */ gnvs->tcrt = 100; /* Temperature at which OS will throttle CPU */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4da8292375cb589d67dc68496b1e81971bc2a61f Gerrit-Change-Number: 49274 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: ACPI: Move common GNVS fields
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Damien Zammit, Angel Pons, Alexander Couzens, Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49273 ) Change subject: ACPI: Move common GNVS fields ...................................................................... ACPI: Move common GNVS fields Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/mp_init.c M src/mainboard/acer/g43t-am3/acpi_tables.c M src/mainboard/asus/p5qc/acpi_tables.c M src/mainboard/asus/p5ql-em/acpi_tables.c M src/mainboard/emulation/qemu-q35/acpi_tables.c M src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c M src/mainboard/intel/dg43gt/acpi_tables.c M src/mainboard/lenovo/t400/acpi_tables.c M src/mainboard/lenovo/x200/acpi_tables.c M src/mainboard/roda/rk9/acpi_tables.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 5 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/49273/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 2cc2e33a..495db63 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -127,6 +127,11 @@ void mp_fill_gnvs(struct global_nvs *gnvs) { gnvs->pcnt = dev_count_cpu(); + gnvs->apic = 1; /* Enable APIC */ + + + /* Enable Multi Processing, c-state/p-state. MPEN */ + gnvs->mpen = gnvs->pcnt > 1 ? 1 : 0; } #endif diff --git a/src/mainboard/acer/g43t-am3/acpi_tables.c b/src/mainboard/acer/g43t-am3/acpi_tables.c index 2bdb744..c85e028 100644 --- a/src/mainboard/acer/g43t-am3/acpi_tables.c +++ b/src/mainboard/acer/g43t-am3/acpi_tables.c @@ -7,6 +7,4 @@ { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ } diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c index 0d0b24c..5063ae6 100644 --- a/src/mainboard/asus/p5qc/acpi_tables.c +++ b/src/mainboard/asus/p5qc/acpi_tables.c @@ -7,7 +7,5 @@ { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c index e678bab..21457ac 100644 --- a/src/mainboard/asus/p5ql-em/acpi_tables.c +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -8,8 +8,6 @@ { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index b95e34c..15f2e56 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -15,8 +15,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c index 78f2ad6..3e06c96 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c @@ -9,7 +9,5 @@ gnvs->lptp = 0; /* LPT port */ gnvs->fdcp = 0; /* Floppy Disk Controller */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/intel/dg43gt/acpi_tables.c b/src/mainboard/intel/dg43gt/acpi_tables.c index 0d0b24c..5063ae6 100644 --- a/src/mainboard/intel/dg43gt/acpi_tables.c +++ b/src/mainboard/intel/dg43gt/acpi_tables.c @@ -7,7 +7,5 @@ { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 643c106a..9c9a951 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -9,8 +9,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 643c106a..9c9a951 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -9,8 +9,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index 1eaadce..2297851 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -9,8 +9,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index a3e2b42..95fb07b 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -651,12 +651,6 @@ return &gnvs->chromeos; } -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ -} - void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 5438b00..e30fd82 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -483,12 +483,6 @@ return sizeof(struct global_nvs); } -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ -} - void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 6144257..25edab1 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -546,12 +546,6 @@ return sizeof(struct global_nvs); } -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ -} - void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 5915fe8..0012097 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -694,12 +694,6 @@ return &gnvs->chromeos; } -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ -} - void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); -- To view, visit https://review.coreboot.org/c/coreboot/+/49273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b Gerrit-Change-Number: 49273 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit January 2021