coreboot-gerrit January 2021

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Change in coreboot[master]: nb/intel/gm45: Guard `CxDRBy_BOUND_SHIFT` macro parameters
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49261 ) Change subject: nb/intel/gm45: Guard `CxDRBy_BOUND_SHIFT` macro parameters ...................................................................... nb/intel/gm45: Guard `CxDRBy_BOUND_SHIFT` macro parameters Wrap `r` in parentheses to avoid unexpected behavior with compound expressions. This prevents `CxDRBy_BOUND_MB(r+1, base)` from triggering undefined behavior when `r = 2`, as the shift would be greater than 32. Change-Id: I14235b2708ab502d842da677451c14203a469b45 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49261 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/gm45/gm45.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 4d8a923..11eeaa5 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -274,7 +274,7 @@ * All registers (4 ranks per channel) have to be set. */ #define CxDRBy_MCHBAR(x, r) (0x1200 + (x * 0x0100) + ((r / 2) * 4)) -#define CxDRBy_BOUND_SHIFT(r) ((r % 2) * 16) +#define CxDRBy_BOUND_SHIFT(r) (((r) % 2) * 16) #define CxDRBy_BOUND_MASK(r) (0x1fc << CxDRBy_BOUND_SHIFT(r)) #define CxDRBy_BOUND_MB(r, b) /* for boundary in MB b */ \ (((b >> 5) << CxDRBy_BOUND_SHIFT(r)) & CxDRBy_BOUND_MASK(r)) -- To view, visit https://review.coreboot.org/c/coreboot/+/49261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14235b2708ab502d842da677451c14203a469b45 Gerrit-Change-Number: 49261 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Enable TC Cold support
by John Zhao (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Enable TC Cold support ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 3 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 21:22:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Enable TC Cold support
by Srinidhi N Kaushik (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Tim Wawrzynczak, John Zhao, Nick Vaccaro, Raj Astekar, Patrick Rudolph. Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Enable TC Cold support ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 3 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 21:12:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] skl: PEG for Optimus
by Benjamin Doron (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40625 ) Change subject: [WIP] skl: PEG for Optimus ...................................................................... Patch Set 15: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/40625/comment/c74ab5c5_15f11e89 PS9, Line 7: PEG > > > PEG usually refers to the PCIe root port that is directly attached to the CPU (PCI device 00:01.0). If this is actually for the PCIe root ports on the PCH, I would be against calling it "PEG" to avoid confusion. > > > > What would you prefer? Note that this attempts to handle both situations, although I cannot test CPU PEG. > > For the commit summary, I would use `ACPI`. Maybe "ACPI device for Optimus?" Also, I'm not sure if Optimus should be mentioned at all; it might also work for AMD's equivalent (but there are Optimus-specific sections). > > > Note that SKL-U, SKL-Y and friends (e.g. KBL) do not have the PEG PCI devices (00:01.0) at all. > > > > > > (FWIW, note that PEG can be bifurcated, in which case additional PCI functions 1 and 2 can be present for PEG) > > > > Would a dGPU have function 2? I am aware that an HDA controller at function 1 is sometimes present. > > I am talking about the PEG PCI devices and functions. I mean that PCI devices 00:01.1 and 00:01.2 can exist sometimes. Okay. They shouldn't be relevant for graphics (I think), but I can add them anyway as part of PEG? File src/soc/intel/skylake/acpi/peg.asl: https://review.coreboot.org/c/coreboot/+/40625/comment/62b386a2_ca33ba96 PS15, Line 7: SKYLAKE_SOC_PCH_H > this is wrong. The Kconfig is about the PCH, not the CPU. […] Also, the way I see this currently, the mainboard DSDT should not include this file if the device is disabled. https://review.coreboot.org/c/coreboot/+/40625/comment/84ff8414_5b6789b4 PS15, Line 13: Skylake See "6th Generation Intel Processor Families for U/Y Platforms" datasheet 2. Section 2.2 lists the device ID for the PEG ports as N/A. > It's ULT parts that do not have PEG. Does "ULT" differ from "mobile?" I can rephrase for clarity. https://review.coreboot.org/c/coreboot/+/40625/comment/a072f72c_880db5be PS15, Line 223: 0x69 > that GPE is likely board specific, is it? It's actually GPE0_PCI_EXP. I'll fix that. https://review.coreboot.org/c/coreboot/+/40625/comment/2098e6ca_c60b764d PS15, Line 234: , > this backups and restores 256 bytes of PCI config space, but that can be accived using OperationRegi […] Right. That would also remove the need to calculate the endpoint's MMIO region. I'm not sure why this is necessary at all. Optimus in the vendor firmware for my board does it conditionally (based on arguments in NVOP - 0x1A: NOUVEAU_DSM_OPTIMUS_CAPS). I'll add debug prints to see when this runs. -- To view, visit https://review.coreboot.org/c/coreboot/+/40625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Gerrit-Change-Number: 40625 Gerrit-PatchSet: 15 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 19:15:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] skl: PEG for Optimus
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Benjamin Doron, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40625 ) Change subject: [WIP] skl: PEG for Optimus ...................................................................... Patch Set 15: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/40625/comment/0c9ff186_4e089fe9 PS9, Line 7: PEG > > PEG usually refers to the PCIe root port that is directly attached to the CPU (PCI device 00:01.0). If this is actually for the PCIe root ports on the PCH, I would be against calling it "PEG" to avoid confusion. > > What would you prefer? Note that this attempts to handle both situations, although I cannot test CPU PEG. For the commit summary, I would use `ACPI`. > > Note that SKL-U, SKL-Y and friends (e.g. KBL) do not have the PEG PCI devices (00:01.0) at all. > > > > (FWIW, note that PEG can be bifurcated, in which case additional PCI functions 1 and 2 can be present for PEG) > > Would a dGPU have function 2? I am aware that an HDA controller at function 1 is sometimes present. I am talking about the PEG PCI devices and functions. I mean that PCI devices 00:01.1 and 00:01.2 can exist sometimes. File src/soc/intel/skylake/acpi/peg.asl: https://review.coreboot.org/c/coreboot/+/40625/comment/9cf0c429_d301060a PS15, Line 7: SKYLAKE_SOC_PCH_H > this is wrong. The Kconfig is about the PCH, not the CPU. […] This is right, because platforms with PCH-H have separate packages for the CPU and PCH, and also have PCIe ports on the CPU. https://review.coreboot.org/c/coreboot/+/40625/comment/26892e05_4e29b4e0 PS15, Line 13: Skylake > mobile sylake do have peg ports It's ULT parts that do not have PEG. -- To view, visit https://review.coreboot.org/c/coreboot/+/40625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Gerrit-Change-Number: 40625 Gerrit-PatchSet: 15 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 18:01:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] skl: PEG for Optimus
by Patrick Rudolph (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Benjamin Doron, Angel Pons. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40625 ) Change subject: [WIP] skl: PEG for Optimus ...................................................................... Patch Set 15: (4 comments) File src/soc/intel/skylake/acpi/peg.asl: https://review.coreboot.org/c/coreboot/+/40625/comment/5d82e202_829856eb PS15, Line 7: SKYLAKE_SOC_PCH_H this is wrong. The Kconfig is about the PCH, not the CPU. All skylake soc should set this, even when the device is disabled. https://review.coreboot.org/c/coreboot/+/40625/comment/39e04bde_935d6f64 PS15, Line 13: Skylake mobile sylake do have peg ports https://review.coreboot.org/c/coreboot/+/40625/comment/da108ae6_257c824e PS15, Line 223: 0x69 that GPE is likely board specific, is it? https://review.coreboot.org/c/coreboot/+/40625/comment/a28fb55d_83bc9fb8 PS15, Line 234: , this backups and restores 256 bytes of PCI config space, but that can be accived using OperationRegion and "PCI_Config" as well. Why is it even necessary to backup and restore registers? -- To view, visit https://review.coreboot.org/c/coreboot/+/40625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Gerrit-Change-Number: 40625 Gerrit-PatchSet: 15 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 10 Jan 2021 17:53:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device: Select VGA_ROM_RUN for non-FSP solution with PCIE DGPU
by Subrata Banik (Code Review) 10 Jan '21

10 Jan '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49016 ) Change subject: device: Select VGA_ROM_RUN for non-FSP solution with PCIE DGPU ...................................................................... device: Select VGA_ROM_RUN for non-FSP solution with PCIE DGPU For onboard graphics initialization, GFX PEIM module inside FSP binary is taking care of graphics initialization based on HAVE_FSP_GOP Kconfig option and input VBT file. Hence no need to load/execute legacy VGA OpROM in order to initialize onboard GFX. In case of non-FSP solution, platform need to select VGA_ROM_RUN Kconfig to perform graphics initialization for PCI-E based discrete card through VGA OpRom (SoC or Mainboard user can't select VGA_ROM_RUN directly because it's part of choice option). TEST=Able to get Pre-OS splash screen with PCI-E DGPU when SoC user doesn't select HAVE_FSP_GOP. Change-Id: Iecb2fcdb105af449bc20ad727759cdef17d5e376 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/device/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/49016/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index a472a6a..b93330c 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -81,7 +81,7 @@ # TODO: Explain differences (if any) for onboard cards. config VGA_ROM_RUN bool "Run VGA Option ROMs" - depends on PCI && (ARCH_X86 || ARCH_PPC64) && !MAINBOARD_FORCE_NATIVE_VGA_INIT + depends on PCI && (ARCH_X86 || ARCH_PPC64) && !HAVE_FSP_GOP && !MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER help Execute VGA Option ROMs in coreboot if found. This can be used -- To view, visit https://review.coreboot.org/c/coreboot/+/49016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecb2fcdb105af449bc20ad727759cdef17d5e376 Gerrit-Change-Number: 49016 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Update GPIOs as per latest schematics
by Subrata Banik (Code Review) 10 Jan '21

10 Jan '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49260 ) Change subject: mb/intel/adlrvp: Update GPIOs as per latest schematics ...................................................................... mb/intel/adlrvp: Update GPIOs as per latest schematics 1. GPP_D8, GPP_H23 => Remove unused GPIOs 2. GPP_E18 .. GPP_E22 => Program the correct Native Functions for GPIO Change-Id: Iedb1f8fbf5f96a9617b72ba1a6419e3fd4e331b4 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49260 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/gpio.c 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 1943a66..3131cc0 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -243,16 +243,16 @@ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D8, NONE), PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2), PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), @@ -265,7 +265,7 @@ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), + PAD_NC(GPP_H23, NONE), /* A21 : HDMI CRLS CTRLCLK */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/49260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedb1f8fbf5f96a9617b72ba1a6419e3fd4e331b4 Gerrit-Change-Number: 49260 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060
by Subrata Banik (Code Review) 10 Jan '21

10 Jan '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49100 ) Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ...................................................................... mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 Enable PCIE RP0 to fix DEKEL FW download failed for x4 controller (PEG 0:6:0). TEST=No FSP error seen while loading DEKEL FW. Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/49100/1 diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 12cd475..4cae2fd 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -69,6 +69,7 @@ register "HybridStorageMode" = "1" # Enable CPU PCIE RP 1 using PEG CLK 0 + register "PcieRpEnable[0]" = "1" register "PcieClkSrcUsage[0]" = "0x40" # Enable PCU PCIE PEG Slot 1 and 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Gerrit-Change-Number: 49100 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Fix wrong comments and typo
by Subrata Banik (Code Review) 10 Jan '21

10 Jan '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49136 ) Change subject: mb/intel/adlrvp: Fix wrong comments and typo ...................................................................... mb/intel/adlrvp: Fix wrong comments and typo 1. CPU -> PCH 2. PCU -> PCH Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/49136/1 diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 12cd475..d3111d8 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -68,10 +68,10 @@ # Hybrid storage mode register "HybridStorageMode" = "1" - # Enable CPU PCIE RP 1 using PEG CLK 0 + # Enable PCH PCIE RP 1 using PEG CLK 0 register "PcieClkSrcUsage[0]" = "0x40" - # Enable PCU PCIE PEG Slot 1 and 2 + # Enable PCH PCIE PEG Slot 1 and 2 register "PcieClkSrcUsage[3]" = "0x41" register "PcieClkSrcUsage[4]" = "0x42" -- To view, visit https://review.coreboot.org/c/coreboot/+/49136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451 Gerrit-Change-Number: 49136 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2021