coreboot-gerrit January 2021

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Change in coreboot[master]: soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE`
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49282 ) Change subject: soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE` ...................................................................... soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE` It is only used in one place, and there's two other equivalent macros. Change-Id: I7c8241e28f688abd2df8180559dd02ee441c7023 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/pmc.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/49282/1 diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index fb5aafd..c252ca1 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -12,7 +12,6 @@ /* Southbridge internal device IO BARs (Set to match FSP settings) */ #define DEFAULT_PMBASE 0x1800 -#define DEFAULT_ACPI_BASE DEFAULT_PMBASE #define ACPI_BASE_ADDRESS DEFAULT_PMBASE #define DEFAULT_TCO_BASE 0x400 diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 8755825..258e6a4 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -16,7 +16,7 @@ /* While we read BAR dynamically in case it changed, let's * initialize it with a same value */ -static u16 acpi_base = DEFAULT_ACPI_BASE; +static u16 acpi_base = ACPI_BASE_ADDRESS; static u32 pwrm_base = DEFAULT_PWRM_BASE; static void pch_power_options(struct device *dev) { /* TODO */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/49282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c8241e28f688abd2df8180559dd02ee441c7023 Gerrit-Change-Number: 49282 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] ChromeOS: Refactor SMBIOS type0 bios_version()
by build bot (Jenkins) (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Lance Zhao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49281 ) Change subject: [WIP] ChromeOS: Refactor SMBIOS type0 bios_version() ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/49281/comment/0a08a728_c7e77a3f PS1, Line 418: if (CONFIG(CHROMEOS)) { trailing statements should be on next line -- To view, visit https://review.coreboot.org/c/coreboot/+/49281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9405afbea29b896488b4cdd6dd32c4db686fe48c Gerrit-Change-Number: 49281 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Comment-Date: Sun, 10 Jan 2021 17:01:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] ChromeOS: Refactor SMBIOS type0 bios_version()
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49281 ) Change subject: [WIP] ChromeOS: Refactor SMBIOS type0 bios_version() ...................................................................... [WIP] ChromeOS: Refactor SMBIOS type0 bios_version() Pointer to an empty string (filled with spaces) is stored inside GNVS and depthcharge fills it in? Change-Id: I9405afbea29b896488b4cdd6dd32c4db686fe48c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/chromeos-gnvs.c M src/arch/x86/smbios.c M src/include/acpi/acpi_gnvs.h 3 files changed, 23 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/49281/1 diff --git a/src/acpi/chromeos-gnvs.c b/src/acpi/chromeos-gnvs.c index 8d96769..ff073f3 100644 --- a/src/acpi/chromeos-gnvs.c +++ b/src/acpi/chromeos-gnvs.c @@ -27,3 +27,13 @@ gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW; } + +void gnvs_set_vbt10(void) +{ + chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs()); + if (!gnvs_chromeos) + return; + + /* Location of smbios_type0.bios_version() string filled with spaces. */ + gnvs_chromeos->vbt10 = smbios_type0_bios_version_address(); +} diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index aaf989d..8ab7c05 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -16,9 +16,6 @@ #include <device/pci_ids.h> #include <device/pci_def.h> #include <device/pci.h> -#if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/gnvs.h> -#endif #include <drivers/vpd/vpd.h> #include <stdlib.h> @@ -398,6 +395,13 @@ return coreboot_version; } +static uintptr_t bios_version_address; + +uintptr_t smbios_type0_bios_version_address(void) +{ + return bios_version_address; +} + static int smbios_write_type0(unsigned long *current, int handle) { struct smbios_type0 *t = (struct smbios_type0 *)*current; @@ -411,11 +415,11 @@ t->vendor = smbios_add_string(t->eos, "coreboot"); t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); -#if CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES) - u32 version_offset = (u32)smbios_string_table_len(t->eos); - /* SMBIOS offsets start at 1 rather than 0 */ - chromeos_get_chromeos_acpi()->vbt10 = (uintptr_t)t->eos + (version_offset - 1); -#endif + if (CONFIG(CHROMEOS)) { + /* SMBIOS offsets start at 1 rather than 0 */ + bios_version_address = (uintptr_t)t->eos; + bios_version_address += (u32)smbios_string_table_len(t->eos) - 1; + } t->bios_version = smbios_add_string(t->eos, get_bios_version()); uint32_t rom_size = CONFIG_ROM_SIZE; rom_size = MIN(CONFIG_ROM_SIZE, 16 * MiB); diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h index b5f65ca..32aaf28 100644 --- a/src/include/acpi/acpi_gnvs.h +++ b/src/include/acpi/acpi_gnvs.h @@ -11,6 +11,7 @@ void gnvs_assign_chromeos(void); void gnvs_set_ecfw_rw(void); +void gnvs_set_vbt10(uintptr_t bios_version); /* Platform code must implement these. */ struct global_nvs; -- To view, visit https://review.coreboot.org/c/coreboot/+/49281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9405afbea29b896488b4cdd6dd32c4db686fe48c Gerrit-Change-Number: 49281 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Use `mp_cpu_bus_init`
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46886 ) Change subject: soc/intel/broadwell: Use `mp_cpu_bus_init` ...................................................................... soc/intel/broadwell: Use `mp_cpu_bus_init` Change-Id: Ic642f32f9c4a269a66ac470b7a7217f20ff8bfba Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/cpu/cpu.c M src/soc/intel/broadwell/cpu/haswell.h M src/soc/intel/broadwell/northbridge.c 3 files changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46886/1 diff --git a/src/soc/intel/broadwell/cpu/cpu.c b/src/soc/intel/broadwell/cpu/cpu.c index 9348439..10db364 100644 --- a/src/soc/intel/broadwell/cpu/cpu.c +++ b/src/soc/intel/broadwell/cpu/cpu.c @@ -614,10 +614,8 @@ .post_mp_init = post_mp_init, }; -void broadwell_init_cpus(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { - struct bus *cpu_bus = dev->link_list; - if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/broadwell/cpu/haswell.h b/src/soc/intel/broadwell/cpu/haswell.h index 399fc23..26077a7 100644 --- a/src/soc/intel/broadwell/cpu/haswell.h +++ b/src/soc/intel/broadwell/cpu/haswell.h @@ -120,8 +120,6 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -void broadwell_init_cpus(struct device *dev); - void set_max_freq(void); /* CPU identification */ diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 980be4d..73c6e83 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -461,7 +461,7 @@ static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = &broadwell_init_cpus, + .init = &mp_cpu_bus_init, }; static void broadwell_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/46886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic642f32f9c4a269a66ac470b7a7217f20ff8bfba Gerrit-Change-Number: 46886 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/parrot: Fix spacing issues
by Felix Singer (Code Review) 10 Jan '21

10 Jan '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49198 ) Change subject: mb/google/parrot: Fix spacing issues ...................................................................... mb/google/parrot: Fix spacing issues Add a space after each comma to fix linter issues. Change-Id: I5533c4fc7aa0e986da4350ec56b84903b3111a07 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/parrot/early_init.c M src/mainboard/google/parrot/ec.c 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/49198/1 diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index f0ffc9f..b7ed73c 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -68,7 +68,7 @@ .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, + .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c index 3aa58c3..f4187eb 100644 --- a/src/mainboard/google/parrot/ec.c +++ b/src/mainboard/google/parrot/ec.c @@ -17,18 +17,18 @@ /* Report EC info */ /* EC version: cmd 0x51 - returns three bytes */ ec_kbc_write_cmd(0x51); - printk(BIOS_DEBUG," EC version %x.%x.%x\n", + printk(BIOS_DEBUG, " EC version %x.%x.%x\n", ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob()); /* EC Project name: cmd 0x52, 0xA0 - returns five bytes */ ec_kbc_write_cmd(0x52); ec_kbc_write_ib(0xA0); - printk(BIOS_DEBUG," EC Project: %c%c%c%c%c\n", - ec_kbc_read_ob(),ec_kbc_read_ob(),ec_kbc_read_ob(), + printk(BIOS_DEBUG, " EC Project: %c%c%c%c%c\n", + ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob()); /* Print the hardware revision */ - printk(BIOS_DEBUG," Parrot Revision %x\n", parrot_rev()); + printk(BIOS_DEBUG, " Parrot Revision %x\n", parrot_rev()); /* US Keyboard */ ec_kbc_write_cmd(0x59); -- To view, visit https://review.coreboot.org/c/coreboot/+/49198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5533c4fc7aa0e986da4350ec56b84903b3111a07 Gerrit-Change-Number: 49198 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezzane: Add a minimal chipset tree
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49245 ) Change subject: soc/amd/cezzane: Add a minimal chipset tree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f Gerrit-Change-Number: 49245 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 10 Jan 2021 15:55:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49241 ) Change subject: superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA ...................................................................... superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA There were several default values given for GPIO data and status registers. As all GPIO are configured as inputs by default, we can't predict the values of these registers, hence set their default values to NANA. Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49241 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Clay Daniels <clay.daniels.jr(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/superiotool/nuvoton.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Clay Daniels: Looks good to me, but someone else must approve diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index d2b72f2..ffd12be 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -538,13 +538,13 @@ {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, {0x07, "GPIO 6, GPIO 7, GPIO 8", {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xec,0xed,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, - {0x00,0x7f,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x00,0x7f,NANA,0x00,NANA,0xff,NANA,0x00,NANA,0x00,0x00,0xff,NANA,0x00,NANA,0x00,EOT}}, {0x08, "WDT1, WDT_MEM, GPIO 0, GPIO 1", {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfe,0xff,EOT}, - {0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x00,0x00,0x00,0xff,NANA,0x00,NANA,0x00,0xff,NANA,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {0x09, "GPIO 2, GPIO 3, GPIO 4, GPIO 5", {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4,0xf5,0xf6,0xf7,0xfe,EOT}, - {0x00,0xff,0x00,0x00,0x00,0x7f,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x00,0xff,NANA,0x00,NANA,0x7f,NANA,0x00,NANA,NANA,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0xff,NANA,0x00,NANA,0x00,EOT}}, {0x0a, "ACPI", {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9,0xec,0xed,0xee,0xf0,0xf2,0xf3,0xf4,0xf6,0xf7,0xfc,0xfe,EOT}, {0x01,0x00,0x00,0x00,0x00,0x02,0x1a,0x00,0x00,0x00,0x00,0x00,0x10,0x5c,0x00,0x00,0x00,0xc0,0x00,0x00,EOT}}, -- To view, visit https://review.coreboot.org/c/coreboot/+/49241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3 Gerrit-Change-Number: 49241 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Clay Daniels <clay.daniels.jr(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Nico Huber, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49241 ) Change subject: superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3 Gerrit-Change-Number: 49241 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Clay Daniels <clay.daniels.jr(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 10 Jan 2021 15:49:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/haswell/haswell.h: Align with Broadwell
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46914 ) Change subject: cpu/intel/haswell/haswell.h: Align with Broadwell ...................................................................... cpu/intel/haswell/haswell.h: Align with Broadwell Sort MSR definitions, move MCHBAR registers to northbridge and relocate C-state latency macros into the header. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/registers/mchbar.h 3 files changed, 52 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/46914/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index deadbc5..284ff01 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -21,22 +21,29 @@ #define CPU_BCLK 100 #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_FEATURE_CONFIG 0x13c -#define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define MSR_LT_LOCK_MEMORY 0x2e7 - #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 - +#define MSR_FEATURE_CONFIG 0x13c +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define MSR_FLEX_RATIO 0x194 +#define FLEX_RATIO_LOCK (1 << 20) +#define FLEX_RATIO_EN (1 << 16) +#define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 #define MSR_POWER_CTL 0x1fc +#define MSR_LT_LOCK_MEMORY 0x2e7 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b @@ -53,7 +60,7 @@ #define IRTL_33554432_NS (5 << 10) #define IRTL_RESPONSE_MASK (0x3ff) -/* long duration in low dword, short duration in high dword */ +/* Long duration in low dword, short duration in high dword */ #define MSR_PKG_POWER_LIMIT 0x610 #define PKG_POWER_LIMIT_MASK 0x7fff #define PKG_POWER_LIMIT_EN (1 << 15) @@ -76,18 +83,6 @@ #define MSR_CONFIG_TDP_CONTROL 0x64b #define MSR_TURBO_ACTIVATION_RATIO 0x64c -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) - -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 - -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) - /* SMM save state MSRs */ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 @@ -96,33 +91,26 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12) +/* Intel suggested latency times in units of 1024ns. */ +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base) * 5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + /* P-state configuration */ #define PSS_MAX_ENTRIES 8 #define PSS_RATIO_STEP 2 #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -/* PCODE MMIO communications live in the MCHBAR. */ -#define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1 << 31) -#define MAILBOX_BIOS_CMD_READ_PCS 1 -#define MAILBOX_BIOS_CMD_WRITE_PCS 2 -#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 -#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 -#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa -#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb -/* Errors are returned back in bits 7:0. */ -#define MAILBOX_BIOS_ERROR_NONE 0 -#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 -#define MAILBOX_BIOS_ERROR_TIMEOUT 2 -#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 -#define MAILBOX_BIOS_ERROR_RESERVED 4 -#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 -#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 -#define MAILBOX_BIOS_ERROR_VR_ERROR 7 -/* Data is passed through bits 31:0 of the data register. */ -#define BIOS_MAILBOX_DATA 0x5da0 - /* Sanity check config options. */ #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) # error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 86a9053..44bbbfd 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -20,20 +20,6 @@ #include "haswell.h" #include "chip.h" -/* Intel suggested latency times in units of 1024ns. */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef - -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) -#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ - C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) - /* * List of supported C-states in this processor. Only the ULT parts support C8, * C9, and C10. diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 97ae433..4bdb49a 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -34,6 +34,28 @@ #define MCH_DDR_POWER_LIMIT_HI 0x58e4 #define SSKPD 0x5d10 /* 64-bit scratchpad register */ + +/* PCODE MMIO communications live in the MCHBAR */ +#define BIOS_MAILBOX_DATA 0x5da0 + +#define BIOS_MAILBOX_INTERFACE 0x5da4 +#define MAILBOX_RUN_BUSY (1 << 31) +#define MAILBOX_BIOS_CMD_READ_PCS 1 +#define MAILBOX_BIOS_CMD_WRITE_PCS 2 +#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 +#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 +#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa +#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb +/* Errors are returned back in bits 7:0 */ +#define MAILBOX_BIOS_ERROR_NONE 0 +#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 +#define MAILBOX_BIOS_ERROR_TIMEOUT 2 +#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 +#define MAILBOX_BIOS_ERROR_RESERVED 4 +#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 +#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 +#define MAILBOX_BIOS_ERROR_VR_ERROR 7 + #define BIOS_RESET_CPL 0x5da8 /* 8-bit */ #define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29 Gerrit-Change-Number: 46914 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/haswell: Align cosmetics with Broadwell
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46913 ) Change subject: cpu/intel/haswell: Align cosmetics with Broadwell ...................................................................... cpu/intel/haswell: Align cosmetics with Broadwell Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3eb522a48edf9e8fc7664141253ae4e2072d71fa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 33 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46913/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 15dcff5..86a9053 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -304,14 +304,15 @@ wrmsr(MSR_VR_MISC_CONFIG, msr); /* Configure VR_MISC_CONFIG2 MSR. */ - if (haswell_is_ult()) { - msr = rdmsr(MSR_VR_MISC_CONFIG2); - msr.lo &= ~0xffff; - /* Allow CPU to control minimum voltage completely (15:8) and - * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ - msr.lo |= 0x006f; - wrmsr(MSR_VR_MISC_CONFIG2, msr); - } + if (!haswell_is_ult()) + return; + + msr = rdmsr(MSR_VR_MISC_CONFIG2); + msr.lo &= ~0xffff; + /* Allow CPU to control minimum voltage completely (15:8) and + * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ + msr.lo |= 0x006f; + wrmsr(MSR_VR_MISC_CONFIG2, msr); } static void configure_pch_power_sharing(void) @@ -382,8 +383,7 @@ u8 power_limit_1_val; if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - - 1; + power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; if (!(msr.lo & PLATFORM_INFO_SET_TDP)) return; @@ -491,26 +491,24 @@ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); - /* Haswell ULT only supoprts the 3-5 latency response registers.*/ - if (haswell_is_ult()) { - /* C-state Interrupt Response Latency Control 3 - package C8 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); + /* Only Haswell ULT supports the 3-5 latency response registers */ + if (!haswell_is_ult()) + return; - /* C-state Interrupt Response Latency Control 4 - package C9 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); + /* C-state Interrupt Response Latency Control 3 - package C8 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); - /* C-state Interrupt Response Latency Control 5 - package C10 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); - } + /* C-state Interrupt Response Latency Control 4 - package C9 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); + + /* C-state Interrupt Response Latency Control 5 - package C10 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } static void configure_thermal_target(void) @@ -595,7 +593,7 @@ } /* All CPUs including BSP will run the following function. */ -static void haswell_init(struct device *cpu) +static void cpu_core_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -640,10 +638,11 @@ initialize_vr_config(); - if (haswell_is_ult()) { - calibrate_24mhz_bclk(); - configure_pch_power_sharing(); - } + if (!haswell_is_ult()) + return; + + calibrate_24mhz_bclk(); + configure_pch_power_sharing(); } static int get_cpu_count(void) @@ -705,7 +704,7 @@ } static struct device_operations cpu_dev_ops = { - .init = haswell_init, + .init = cpu_core_init, }; static const struct cpu_device_id cpu_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/46913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3eb522a48edf9e8fc7664141253ae4e2072d71fa Gerrit-Change-Number: 46913 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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