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Change in coreboot[master]: sb/intel: Factor out soc_fill_gnvs()
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48706 ) Change subject: sb/intel: Factor out soc_fill_gnvs() ...................................................................... sb/intel: Factor out soc_fill_gnvs() Name the common part of GNVS initialisation as soc_fill_gnvs(). It is also moved before the call to acpi_create_gnvs(), which followup will rename to mainbord_fill_gnvs() to reflect that implementation is under mb/. Change-Id: Ic4cf1548b65a86212d6e45d460fcd23bb8036365 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/gnvs.c M src/include/acpi/acpi_gnvs.h M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 8 files changed, 60 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/48706/1 diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index 40c9745..e572a37 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -29,6 +29,8 @@ *gnvs_cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); } +__weak void soc_fill_gnvs(struct global_nvs *gnvs_) { } + void *gnvs_get_or_create(void) { size_t gnvs_size; diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h index 6173fa1..d827a07 100644 --- a/src/include/acpi/acpi_gnvs.h +++ b/src/include/acpi/acpi_gnvs.h @@ -33,4 +33,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs); void acpi_init_gnvs(struct global_nvs *gnvs); +void soc_fill_gnvs(struct global_nvs *gnvs); + #endif diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index bf11bcf..fb37789 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -15,7 +15,6 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <cpu/x86/smm.h> -#include <cbmem.h> #include <string.h> #include "chip.h" #include "pch.h" @@ -642,25 +641,23 @@ pch_enable(dev); } +void soc_fill_gnvs(struct global_nvs *gnvs) +{ + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); +} + void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - if (gnvs) { + soc_fill_gnvs(gnvs); + acpi_create_gnvs(gnvs); - acpi_create_gnvs(gnvs); - - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - - - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } + acpi_inject_nvsa(); } static const char *lpc_acpi_name(const struct device *dev) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index f6fc384..83f548f 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -16,7 +16,6 @@ #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <string.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/pmbase.h> @@ -479,23 +478,21 @@ outb(POST_OS_BOOT, 0x80); } +void soc_fill_gnvs(struct global_nvs *gnvs) +{ + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ +} + void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - if (gnvs) { - - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - - acpi_create_gnvs(gnvs); - - - /* Add it to SSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } + soc_fill_gnvs(gnvs); + acpi_create_gnvs(gnvs); + acpi_inject_nvsa(); } static const char *lpc_acpi_name(const struct device *dev) diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index f587d01..064d79e 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -15,7 +15,6 @@ #include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> -#include <cbmem.h> #include <string.h> #include "chip.h" #include "i82801ix.h" @@ -456,16 +455,11 @@ void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - if (gnvs) { - acpi_create_gnvs(gnvs); - - - /* Add it to SSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); - acpigen_pop_len(); - } + acpi_create_gnvs(gnvs); + acpi_inject_nvsa(); } static const char *lpc_acpi_name(const struct device *dev) diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 75cc7f4..d959120 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -16,7 +16,6 @@ #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <string.h> #include "chip.h" #include "i82801jx.h" @@ -480,16 +479,11 @@ void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - if (gnvs) { - acpi_create_gnvs(gnvs); - - - /* Add it to SSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } + acpi_create_gnvs(gnvs); + acpi_inject_nvsa(); } static const char *lpc_acpi_name(const struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 5f31c43..4f2f018 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -16,7 +16,6 @@ #include <acpi/acpi_gnvs.h> #include <elog.h> #include <acpi/acpigen.h> -#include <cbmem.h> #include <string.h> #include <cpu/x86/smm.h> #include "chip.h" @@ -542,24 +541,23 @@ pch_enable(dev); } +void soc_fill_gnvs(struct global_nvs *gnvs) +{ + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); +} + void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - if (gnvs) { + soc_fill_gnvs(gnvs); + acpi_create_gnvs(gnvs); - acpi_create_gnvs(gnvs); - - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - - - /* Add it to SSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); - acpigen_pop_len(); - } + acpi_inject_nvsa(); } static const char *lpc_acpi_name(const struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 102dc08..de7cc23 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -13,7 +13,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> -#include <cbmem.h> #include <string.h> #include "chip.h" #include "iobp.h" @@ -680,24 +679,23 @@ pch_enable(dev); } +void soc_fill_gnvs(struct global_nvs *gnvs) +{ + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); +} + void southbridge_inject_dsdt(const struct device *dev) { - struct global_nvs *gnvs; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + soc_fill_gnvs(gnvs); + acpi_create_gnvs(gnvs); - if (gnvs) { - acpi_create_gnvs(gnvs); - - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32)gnvs); - acpigen_pop_len(); - } + acpi_inject_nvsa(); } static const char *lpc_acpi_name(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/48706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4cf1548b65a86212d6e45d460fcd23bb8036365 Gerrit-Change-Number: 48706 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: ACPI: Replace uses of CBMEM_ID_ACPI_GNVS
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48705 ) Change subject: ACPI: Replace uses of CBMEM_ID_ACPI_GNVS ...................................................................... ACPI: Replace uses of CBMEM_ID_ACPI_GNVS Change-Id: I45a2d9cb7f07609a1ff03fd70f17c3f2d4f013b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/skylake/acpi.c 6 files changed, 36 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/48705/1 diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index d8305c6..428002b 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -7,7 +7,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <bootstate.h> -#include <cbmem.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <device/device.h> @@ -486,18 +485,13 @@ static void southcluster_inject_dsdt(const struct device *device) { - struct global_nvs *gnvs; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + acpi_create_gnvs(gnvs); - if (gnvs) { - acpi_create_gnvs(gnvs); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } + acpi_inject_nvsa(); } static struct device_operations device_ops = { diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 5880d1b..588c7e8 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -5,7 +5,6 @@ #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> @@ -366,18 +365,13 @@ void southcluster_inject_dsdt(const struct device *device) { - struct global_nvs *gnvs; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + acpi_create_gnvs(gnvs); - if (gnvs) { - acpi_create_gnvs(gnvs); - - /* Add it to DSDT */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } + acpi_inject_nvsa(); } __weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 8036210..c328a90 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -12,9 +12,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> -#include <cbmem.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <string.h> #include <soc/gpio.h> #include <soc/iobp.h> @@ -605,24 +602,20 @@ static void southcluster_inject_dsdt(const struct device *device) { - struct global_nvs *gnvs; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); +#if 0 + /* Set unknown wake source */ + gnvs->pm1i = -1; - if (gnvs) { - acpi_create_gnvs(gnvs); + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); +#endif - /* Set unknown wake source */ - gnvs->pm1i = -1; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } + acpi_create_gnvs(gnvs); + acpi_inject_nvsa(); } static unsigned long broadwell_write_acpi_tables(const struct device *device, diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 52143a2..9dabcb8 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -221,18 +221,12 @@ void southbridge_inject_dsdt(const struct device *device) { - struct global_nvs *gnvs; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs) { - acpi_create_gnvs(gnvs); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t) gnvs); - acpigen_pop_len(); - } + acpi_create_gnvs(gnvs); + acpi_inject_nvsa(); } static int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 1a97ae5..cf30541 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -242,18 +242,12 @@ void southcluster_inject_dsdt(const struct device *device) { - struct global_nvs *gnvs; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs) { - acpi_create_gnvs(gnvs); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32)gnvs); - acpigen_pop_len(); - } + acpi_create_gnvs(gnvs); + acpi_inject_nvsa(); } __weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 4de8c5c..315e5f8 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -523,18 +523,12 @@ void southbridge_inject_dsdt(const struct device *device) { - struct global_nvs *gnvs; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs) { - acpi_create_gnvs(gnvs); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) (uintptr_t)gnvs); - acpigen_pop_len(); - } + acpi_create_gnvs(gnvs); + acpi_inject_nvsa(); } /* Save wake source information for calculating ACPI _SWS values */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45a2d9cb7f07609a1ff03fd70f17c3f2d4f013b9 Gerrit-Change-Number: 48705 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/braswell: Refactor acpi_init_gnvs()
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48704 ) Change subject: soc/intel/braswell: Refactor acpi_init_gnvs() ...................................................................... soc/intel/braswell: Refactor acpi_init_gnvs() Move GNVS details to different function, called from acpi_create_gnvs(). Change-Id: Ief02c078fe37753c0d29418394a351105a1aacc8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/braswell/acpi.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/48704/1 diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 9c4e83a..5880d1b 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -69,6 +69,12 @@ /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); + + /* Fill in the Wi-Fi Region ID */ + if (CONFIG(HAVE_REGULATORY_DOMAIN)) + gnvs->cid1 = wifi_regulatory_domain(); + else + gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; } int acpi_sci_irq(void) @@ -367,12 +373,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); - /* Fill in the Wi-Fi Region ID */ - if (CONFIG(HAVE_REGULATORY_DOMAIN)) - gnvs->cid1 = wifi_regulatory_domain(); - else - gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; - /* Add it to DSDT */ acpigen_write_scope("\\"); acpigen_write_name_dword("NVSA", (u32) gnvs); -- To view, visit https://review.coreboot.org/c/coreboot/+/48704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief02c078fe37753c0d29418394a351105a1aacc8 Gerrit-Change-Number: 48704 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/x/acpi_tables: Move EC_RW detection
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48777 ) Change subject: mb/x/acpi_tables: Move EC_RW detection ...................................................................... mb/x/acpi_tables: Move EC_RW detection These boards without ChromeEC do not set ACTIVE_EC_RW flag as part of the gnvs_assign_chromeos() function. Create abstraction to avoid <vendorcode/chromeos/x> include. Change-Id: Ic6029e1807fcfe7dd2c766ce8221e347b6b096f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/chromeos-gnvs.c M src/include/acpi/acpi_gnvs.h M src/mainboard/google/beltino/acpi_tables.c M src/mainboard/google/butterfly/acpi_tables.c M src/mainboard/google/parrot/acpi_tables.c M src/mainboard/google/stout/acpi_tables.c M src/mainboard/intel/baskingridge/acpi_tables.c M src/mainboard/intel/emeraldlake2/acpi_tables.c M src/mainboard/samsung/lumpy/acpi_tables.c M src/mainboard/samsung/stumpy/acpi_tables.c 10 files changed, 22 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/48777/1 diff --git a/src/acpi/chromeos-gnvs.c b/src/acpi/chromeos-gnvs.c index b1588fa..8d96769 100644 --- a/src/acpi/chromeos-gnvs.c +++ b/src/acpi/chromeos-gnvs.c @@ -18,3 +18,12 @@ if (CONFIG(EC_GOOGLE_CHROMEEC) && !google_ec_running_ro()) gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW; } + +void gnvs_set_ecfw_rw(void) +{ + chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs()); + if (!gnvs_chromeos) + return; + + gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW; +} diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h index 1da6fd4..32a1ff6 100644 --- a/src/include/acpi/acpi_gnvs.h +++ b/src/include/acpi/acpi_gnvs.h @@ -11,6 +11,12 @@ void gnvs_assign_chromeos(void); +#if CONFIG(CHROMEOS) +void gnvs_set_ecfw_rw(void); +#else +static inline void gnvs_set_ecfw_rw(void) { } +#endif + /* Platform code must implement these. */ struct global_nvs; size_t gnvs_size_of_array(void); diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 9756695..9d1f4dd 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -3,10 +3,8 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <device/device.h> -#include <ec/google/chromeec/ec.h> #include <southbridge/intel/lynxpoint/nvs.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <variant/thermal.h> void acpi_create_gnvs(struct global_nvs *gnvs) @@ -22,11 +20,6 @@ /* TPM Present */ gnvs->tpmp = 1; -#if CONFIG(CHROMEOS) - // SuperIO is always RO - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif - gnvs->f4of = FAN4_THRESHOLD_OFF; gnvs->f4on = FAN4_THRESHOLD_ON; gnvs->f4pw = FAN4_PWM; diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index 315fd6d..110966a 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -2,7 +2,6 @@ #include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -#include <vendorcode/google/chromeos/gnvs.h> #include "thermal.h" void acpi_create_gnvs(struct global_nvs *gnvs) @@ -19,7 +18,7 @@ // The firmware read/write status is a "virtual" switch and // will be handled elsewhere. Until then hard-code to // read/write instead of read-only for developer mode. - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RW; + gnvs_set_ecfw_rw(); // the lid is open by default. gnvs->lids = 1; @@ -27,5 +26,4 @@ /* EC handles all thermal and fan control on Butterfly. */ gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; - } diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 62e52c4..1d20c79 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <device/device.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <ec/compal/ene932/ec.h> #include "ec.h" @@ -22,10 +21,8 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; -#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = parrot_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif + if (!parrot_ec_running_ro()) + gnvs_set_ecfw_rw(); /* EC handles all active thermal and fan control on Parrot. */ gnvs->tcrt = CRITICAL_TEMPERATURE; diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index f994e57..cf362d8 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <device/device.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <bootmode.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" @@ -23,10 +22,8 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; -#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = get_recovery_mode_switch() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif + if (!get_recovery_mode_switch()) + gnvs_set_ecfw_rw(); /* EC handles all thermal and fan control on Stout. */ gnvs->tcrt = CRITICAL_TEMPERATURE; diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index c0c488a..1d915a1 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <device/device.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/nvs.h> @@ -25,11 +24,6 @@ /* TPM Present */ gnvs->tpmp = 1; -#if CONFIG(CHROMEOS) - /* Emerald Lake has no EC (?) */ - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif - gnvs->f4of = FAN4_THRESHOLD_OFF; gnvs->f4on = FAN4_THRESHOLD_ON; gnvs->f4pw = FAN4_PWM; diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 302966a..d133249 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <device/device.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> #include "thermal.h" @@ -44,7 +43,4 @@ gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; gnvs->tmax = MAX_TEMPERATURE; - - // Stumpy has no arms^H^H^H^HEC. - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 1a3317d..b26f5c8 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -4,9 +4,6 @@ #include <acpi/acpi_gnvs.h> #include <device/device.h> #include <ec/acpi/ec.h> -#if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/gnvs.h> -#endif #include <southbridge/intel/bd82x6x/nvs.h> #include "thermal.h" @@ -47,5 +44,6 @@ gnvs->tmax = MAX_TEMPERATURE; gnvs->flvl = 5; - gnvs->chromeos.vbt2 = ec_read(0xcb) ? ACTIVE_ECFW_RW : ACTIVE_ECFW_RO; + if (ec_read(0xcb)) + gnvs_set_ecfw_rw(); } diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index b2c1fca..b046c2c 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <device/device.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> #include "thermal.h" @@ -45,7 +44,4 @@ gnvs->tpsv = PASSIVE_TEMPERATURE; gnvs->tmax = MAX_TEMPERATURE; gnvs->flvl = 5; - - // Stumpy has no arms^H^H^H^HEC. - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6029e1807fcfe7dd2c766ce8221e347b6b096f9 Gerrit-Change-Number: 48777 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: ACPI: Drop redundant ChromeOS setup for GNVS
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48703 ) Change subject: ACPI: Drop redundant ChromeOS setup for GNVS ...................................................................... ACPI: Drop redundant ChromeOS setup for GNVS Already done in common gnvs_get_or_create() implementation. Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/link/acpi_tables.c M src/mainboard/google/slippy/acpi_tables.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 18 files changed, 0 insertions(+), 161 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/48703/1 diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index f37f37e..5b0621e 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -2,8 +2,6 @@ #include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include "thermal.h" void acpi_create_gnvs(struct global_nvs *gnvs) @@ -16,11 +14,6 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; -#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->tmps = CTDP_SENSOR_ID; gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF; diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 666143c..fcafd88 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -3,8 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <device/device.h> -#include <vendorcode/google/chromeos/gnvs.h> -#include <ec/google/chromeec/ec.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/nvs.h> @@ -23,11 +21,6 @@ /* TPM Present */ gnvs->tpmp = 1; -#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->tmps = TEMPERATURE_SENSOR_ID; gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 46a9de7..f40c778 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -395,12 +395,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index aadf3a2..dd8f29f 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -164,12 +164,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 4ebe0d5..e188fa6 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -289,16 +289,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 0a9b16e..92d1daf 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -77,12 +77,6 @@ struct soc_intel_apollolake_config *cfg; cfg = config_of_soc(); - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Set unknown wake source */ gnvs->pm1i = ~0ULL; diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index fdf7698..e8ef46f 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -20,9 +20,6 @@ #include <soc/pattrs.h> #include <soc/pm.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> - #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \ @@ -68,17 +65,6 @@ /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } } int acpi_sci_irq(void) diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index e52ea8a..9c4e83a 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -11,7 +11,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> #include <device/pci.h> -#include <ec/google/chromeec/ec.h> #include <drivers/intel/gma/opregion.h> #include <soc/acpi.h> #include <soc/gfx.h> @@ -23,7 +22,6 @@ #include <soc/pm.h> #include <string.h> #include <types.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> #define MWAIT_RES(state, sub_state) \ @@ -71,17 +69,6 @@ /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } } int acpi_sci_irq(void) diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 9b5ac9e..dbaade6 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -14,8 +14,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 4d4d861..8036210 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -618,17 +618,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } - /* Add it to DSDT. */ acpigen_write_scope("\\"); acpigen_write_name_dword("NVSA", (u32) gnvs); diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 1d4419b..0a09cd4 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -8,7 +8,6 @@ #include <console/console.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -20,7 +19,6 @@ #include <soc/pm.h> #include <soc/systemagent.h> #include <string.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> #include "chip.h" @@ -194,17 +192,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 6d76b66..295a91a 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -257,16 +257,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 30917f3..565dc65 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -6,7 +6,6 @@ #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -18,7 +17,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <string.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> /* @@ -189,16 +187,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 1591953..8494911 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -9,7 +9,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -284,16 +283,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 6db7dc1..4de8c5c 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -12,7 +12,6 @@ #include <cpu/x86/msr.h> #include <cpu/intel/common/common.h> #include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/sgx.h> @@ -29,7 +28,6 @@ #include <soc/systemagent.h> #include <string.h> #include <types.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> #include <device/pci_ops.h> @@ -167,17 +165,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index f21953d..7f15a96 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -284,16 +283,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index edde09e..bf11bcf 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -654,9 +654,6 @@ gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); -#if CONFIG(CHROMEOS) - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#endif /* Add it to DSDT. */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 739a3c2..102dc08 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -693,12 +693,6 @@ gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); -#if CONFIG(CHROMEOS) - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#endif - - - /* Add it to DSDT. */ acpigen_write_scope("\\"); acpigen_write_name_dword("NVSA", (u32)gnvs); -- To view, visit https://review.coreboot.org/c/coreboot/+/48703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Gerrit-Change-Number: 48703 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: ACPI: Drop redundant CONSOLE_CBMEM setup in GNVS
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48702 ) Change subject: ACPI: Drop redundant CONSOLE_CBMEM setup in GNVS ...................................................................... ACPI: Drop redundant CONSOLE_CBMEM setup in GNVS Already done in common gnvs_get_or_create() implementation. Change-Id: I77c292cd9590d7fc54d8b21ea62717a2d77e5ba4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/southbridge/intel/lynxpoint/lpc.c 16 files changed, 0 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/48702/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 46a3cb0..46a9de7 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -395,10 +395,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - - if (CONFIG(CONSOLE_CBMEM)) - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&gnvs->chromeos); diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 74a3b2f..aadf3a2 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -164,10 +164,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - - if (CONFIG(CONSOLE_CBMEM)) - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&gnvs->chromeos); diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index ca5d726..4ebe0d5 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -289,10 +289,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CONSOLE_CBMEM)) - /* Update the mem console pointer. */ - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 61d42a5..0a9b16e 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -77,10 +77,6 @@ struct soc_intel_apollolake_config *cfg; cfg = config_of_soc(); - - if (CONFIG(CONSOLE_CBMEM)) - gnvs->cbmc = (uintptr_t) cbmem_find(CBMEM_ID_CONSOLE); - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&gnvs->chromeos); diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 1144749..fdf7698 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -69,11 +69,6 @@ /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 9968520..e52ea8a 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -72,11 +72,6 @@ /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index c735a81..4d4d861 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -618,11 +618,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index f061c30..1d4419b 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -194,10 +194,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - /* Update the mem console pointer. */ - if (CONFIG(CONSOLE_CBMEM)) - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index f46f1fc..1a97ae5 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -67,11 +67,6 @@ /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = (uintptr_t)cbmem_top(); -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - /* MMIO Low/High & TSEG base and length */ gnvs->mmiob = (u32)get_top_of_low_memory(); gnvs->mmiol = (u32)(get_pciebase() - 1); diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index af837ab..6d76b66 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -257,10 +257,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CONSOLE_CBMEM)) - /* Update the mem console pointer. */ - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index ff66300..30917f3 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -189,10 +189,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CONSOLE_CBMEM)) - /* Update the mem console pointer. */ - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 8673da1..1591953 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -284,10 +284,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CONSOLE_CBMEM)) - /* Update the mem console pointer. */ - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 50175aa..6db7dc1 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -167,11 +167,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)(uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); -#endif - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index c7c5446..f21953d 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -284,10 +284,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CONSOLE_CBMEM)) - /* Update the mem console pointer. */ - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 53b9d27..e98ee08 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -31,10 +31,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); - - /* Update the mem console pointer. */ - if (CONFIG(CONSOLE_CBMEM)) - gnvs->cbmc = (uint32_t)cbmem_find(CBMEM_ID_CONSOLE); } int soc_madt_sci_irq_polarity(int sci) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 26d7c48..739a3c2 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -697,8 +697,6 @@ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #endif - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); /* Add it to DSDT. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77c292cd9590d7fc54d8b21ea62717a2d77e5ba4 Gerrit-Change-Number: 48702 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocations
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48701 ) Change subject: ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocations ...................................................................... ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocations Allocation now happens prior to device enumeration. The step cbmem_add() is a no-op here, if reached for some boards. The memset() here is also redundant and becomes harmful with followup works, as it would wipe out the CBMEM console and ChromeOS related fields without them being set again. Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/protectli/vault_bsw/acpi_tables.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/baytrail/ramstage.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/ramstage.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/ramstage.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 22 files changed, 14 insertions(+), 114 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/48701/1 diff --git a/src/mainboard/protectli/vault_bsw/acpi_tables.c b/src/mainboard/protectli/vault_bsw/acpi_tables.c index c40769a..5267dcd 100644 --- a/src/mainboard/protectli/vault_bsw/acpi_tables.c +++ b/src/mainboard/protectli/vault_bsw/acpi_tables.c @@ -7,7 +7,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); acpi_init_gnvs(gnvs); diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 107aa4af..96fb176 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -100,7 +100,6 @@ static void lpc_read_resources(struct device *dev) { struct resource *res; - struct global_nvs *gnvs; /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -134,10 +133,6 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; compact_resources(dev); - - /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - printk(BIOS_DEBUG, "ACPI GNVS at %p\n", gnvs); } static void lpc_set_resources(struct device *dev) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 17940e9..46a3cb0 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -395,8 +395,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - /* Clear out GNVS. */ - memset(gnvs, 0, sizeof(*gnvs)); if (CONFIG(CONSOLE_CBMEM)) gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index e62f235..74a3b2f 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -164,8 +164,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - /* Clear out GNVS. */ - memset(gnvs, 0, sizeof(*gnvs)); if (CONFIG(CONSOLE_CBMEM)) gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index d0e7a73..61d42a5 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -77,8 +77,6 @@ struct soc_intel_apollolake_config *cfg; cfg = config_of_soc(); - /* Clear out GNVS. */ - memset(gnvs, 0, sizeof(*gnvs)); if (CONFIG(CONSOLE_CBMEM)) gnvs->cbmc = (uintptr_t) cbmem_find(CBMEM_ID_CONSOLE); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index a4ed8bd..3d5c1ab 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -315,9 +315,6 @@ */ p2sb_unhide(); - /* Allocate ACPI NVS in CBMEM */ - cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { printk(BIOS_INFO, "Skip setting RAPL per configuration\n"); } else { diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index b15970e..e199e9f 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -2,6 +2,7 @@ #include <arch/cpu.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> @@ -143,15 +144,9 @@ static void s3_resume_prepare(void) { - struct global_nvs *gnvs; + struct global_nvs *gnvs = acpi_get_gnvs(); - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - if (gnvs == NULL) - return; - - if (!acpi_is_wakeup_s3()) - memset(gnvs, 0, sizeof(struct global_nvs)); - else + if (gnvs && acpi_is_wakeup_s3()) s3_save_acpi_wake_source(gnvs); } diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 2df6410..d8305c6 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -489,11 +489,6 @@ struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } if (gnvs) { acpi_create_gnvs(gnvs); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 9577536..9968520 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -381,11 +381,6 @@ struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } if (gnvs) { acpi_create_gnvs(gnvs); diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index eba1527..68bddfb 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -2,6 +2,7 @@ #include <arch/cpu.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> @@ -135,24 +136,11 @@ return 1; } -static void s3_resume_prepare(void) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - if (!acpi_is_wakeup_s3() && gnvs) - memset(gnvs, 0, sizeof(struct global_nvs)); -} - static void set_board_id(void) { - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) return; - } gnvs->bdid = board_id(); } @@ -165,9 +153,6 @@ /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); - /* Indicate S3 resume to rest of ramstage. */ - s3_resume_prepare(); - /* Perform silicon specific init. */ intel_silicon_init(); set_max_freq(); diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 5a29b02..c735a81 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -593,8 +593,6 @@ static void pch_lpc_read_resources(struct device *dev) { - struct global_nvs *gnvs; - /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -603,11 +601,6 @@ /* Add IO resources. */ pch_lpc_add_io_resources(dev); - - /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - if (!acpi_is_wakeup_s3() && gnvs) - memset(gnvs, 0, sizeof(struct global_nvs)); } static void southcluster_inject_dsdt(const struct device *device) @@ -615,11 +608,6 @@ struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } if (gnvs) { acpi_create_gnvs(gnvs); diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 57abf95..214830d 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -63,15 +63,9 @@ static void s3_resume_prepare(void) { - struct global_nvs *gnvs; + struct global_nvs *gnvs = acpi_get_gnvs(); - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - if (gnvs == NULL) - return; - - if (!acpi_is_wakeup_s3()) - memset(gnvs, 0, sizeof(struct global_nvs)); - else + if (gnvs && acpi_is_wakeup_s3()) save_acpi_wake_source(gnvs); } diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 69f7a59..52143a2 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/cpu.h> #include <arch/ioapic.h> @@ -7,7 +8,6 @@ #include <bootstate.h> #include <cbmem.h> #include <cf9_reset.h> -#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/intel/turbo.h> #include <cpu/intel/common/common.h> @@ -224,11 +224,6 @@ struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } if (gnvs) { acpi_create_gnvs(gnvs); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 2a847ed..f46f1fc 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -250,11 +250,6 @@ struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } if (gnvs) { acpi_create_gnvs(gnvs); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index d654a58..50175aa 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -544,11 +544,6 @@ struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } if (gnvs) { acpi_create_gnvs(gnvs); diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 184eb6b..14d37f7 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -208,11 +208,6 @@ struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } if (gnvs) { acpi_create_gnvs(gnvs); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 4515261..edde09e 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -644,10 +644,9 @@ void southbridge_inject_dsdt(const struct device *dev) { - struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = acpi_get_gnvs(); if (gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 4db9351..f6fc384 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -481,10 +481,9 @@ void southbridge_inject_dsdt(const struct device *dev) { - struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = acpi_get_gnvs(); if (gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 821a0b7..f587d01 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -455,10 +455,9 @@ void southbridge_inject_dsdt(const struct device *dev) { - struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = acpi_get_gnvs(); if (gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ad9bac1..75cc7f4 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -479,10 +479,9 @@ void southbridge_inject_dsdt(const struct device *dev) { - struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = acpi_get_gnvs(); if (gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 0895ddd..5f31c43 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -544,10 +544,9 @@ void southbridge_inject_dsdt(const struct device *dev) { - struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = acpi_get_gnvs(); if (gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 586e626..26d7c48 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -661,8 +661,6 @@ static void pch_lpc_read_resources(struct device *dev) { - struct global_nvs *gnvs; - /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -671,11 +669,6 @@ /* Add IO resources. */ pch_lpc_add_io_resources(dev); - - /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - if (!acpi_is_wakeup_s3() && gnvs) - memset(gnvs, 0, sizeof(struct global_nvs)); } static void pch_lpc_enable(struct device *dev) @@ -692,11 +685,6 @@ struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } if (gnvs) { acpi_create_gnvs(gnvs); -- To view, visit https://review.coreboot.org/c/coreboot/+/48701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f Gerrit-Change-Number: 48701 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

6 24

Change in coreboot[master]: This change implements CrashLog for intel TGL.
by Lance Zhao (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Francois Toguo Fotso, Martin Roth, Nikunj Dadhania, Patrick Rudolph. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49258 ) Change subject: This change implements CrashLog for intel TGL. ...................................................................... Patch Set 5: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49258/comment/ca990207_1c3efd8c PS5, Line 9: Intel based platforms It is not supported on all Intel platform, please make more specific. https://review.coreboot.org/c/coreboot/+/49258/comment/646c5744_73afe11a PS5, Line 14: Built, crashLog data generated, extracted, processed, decoded sucessfully. Test had been done which platform need to mentioned, is that Tigerlake RVP platform? Patchset: PS5: At least please separated the commit into ACPI BERT table related,and how TGL implement the feature File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/49258/comment/9b8a5ae0_86fc47ee PS5, Line 1557: current += bert->header.length; We may need a current = acpi_align_current(current); after Current had been updated. File src/include/cper.h: https://review.coreboot.org/c/coreboot/+/49258/comment/fbeb1991_887a8b1f PS5, Line 384: __packed Packed needed here? -- To view, visit https://review.coreboot.org/c/coreboot/+/49258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a4422ca5a61e2dac71cf46ca22ed793891ef85a Gerrit-Change-Number: 49258 Gerrit-PatchSet: 5 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 07:45:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: This change implements CrashLog for intel TGL.
by Francois Toguo Fotso (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Martin Roth, Francois Toguo Fotso, Nikunj Dadhania, Patrick Rudolph. Francois Toguo Fotso has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49258 ) Change subject: This change implements CrashLog for intel TGL. ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/49258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a4422ca5a61e2dac71cf46ca22ed793891ef85a Gerrit-Change-Number: 49258 Gerrit-PatchSet: 5 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 01:00:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: acpi,soc/intel/common: add support for Intel Low Power Idle Table
by Tim Wawrzynczak (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Michael Niewöhner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49045 ) Change subject: acpi,soc/intel/common: add support for Intel Low Power Idle Table ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e Gerrit-Change-Number: 49045 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sat, 09 Jan 2021 22:53:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2021