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Change in coreboot[master]: [WIP] ACPI GNVS: Move dev_count_cpu()
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Jason Glenesk, Mariusz Szafrański, Marshall Dawson, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Andrey Petrov, Patrick Rudolph, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49272 ) Change subject: [WIP] ACPI GNVS: Move dev_count_cpu() ...................................................................... [WIP] ACPI GNVS: Move dev_count_cpu() Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/mp_init.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 20 files changed, 7 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/49272/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 01c1d5f..2cc2e33a 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -123,6 +123,13 @@ static int global_num_aps; static struct mp_flight_plan mp_info; +#if 0 +void mp_fill_gnvs(struct global_nvs *gnvs) +{ + gnvs->pcnt = dev_count_cpu(); +} +#endif + /* Keep track of device structure for each CPU. */ static struct device *cpus_dev[CONFIG_MAX_CPUS]; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 743b32c..70c93c4 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -399,9 +399,6 @@ /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); } void southbridge_inject_dsdt(const struct device *device) diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index dd8f29f..e956e66 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -167,9 +167,6 @@ /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); } void southbridge_inject_dsdt(const struct device *device) diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 663eecb..d1ab6a0 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -285,9 +285,6 @@ /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 63787ed..773f56e 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -80,9 +80,6 @@ /* Set unknown wake source */ gnvs->pm1i = ~0ULL; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = cfg->dptf_enable; diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index cf031b9..d379beb 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -61,9 +61,6 @@ /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); } diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index caeae39..0be5ca6 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -64,9 +64,6 @@ /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 03a6872..5111601 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -604,9 +604,6 @@ { /* Set unknown wake source */ gnvs->pm1i = -1; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); } static void southcluster_inject_dsdt(const struct device *device) diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index b8fa9a7..bfb719f 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -189,9 +189,6 @@ /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 8ef2faa..3753bd9 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -62,9 +62,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) { - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = (uintptr_t)cbmem_top(); diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 4ea3e25..88336fe 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -253,9 +253,6 @@ /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index a9e56fa..4a84446 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -184,9 +184,6 @@ /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index e480f55..ea5fb0b 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -280,9 +280,6 @@ /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 2406dc5..38308e4 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -163,9 +163,6 @@ /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 69b7b17..354e3d2 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -280,9 +280,6 @@ /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 9d5f47b..99326ee 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <assert.h> @@ -14,7 +13,6 @@ #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/msr.h> -#include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_util.h> @@ -28,13 +26,6 @@ return current; } -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); -} - int soc_madt_sci_irq_polarity(int sci) { if (sci >= 20) diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index a7050f0..330f473 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <assert.h> @@ -14,7 +13,6 @@ #include <soc/iomap.h> #include <device/mmio.h> #include <soc/msr.h> -#include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_util.h> @@ -28,13 +26,6 @@ return current; } -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); -} - int soc_madt_sci_irq_polarity(int sci) { if (sci >= 20) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index bb1ab6b..a3e2b42 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -655,7 +655,6 @@ { gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); } void southbridge_inject_dsdt(const struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 3f59a19..6144257 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -550,7 +550,6 @@ { gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); } void southbridge_inject_dsdt(const struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 05593b1..5915fe8 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -698,7 +698,6 @@ { gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); } void southbridge_inject_dsdt(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/49272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783 Gerrit-Change-Number: 49272 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Change some SMI logging
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49249 to look at the new patch set (#3). Change subject: sb/intel/common: Change some SMI logging ...................................................................... sb/intel/common: Change some SMI logging Change-Id: Ief0c3d36e6de6e18b7f2613f043ac4d31a193f9d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/dell/optiplex_9010/smihandler.c M src/mainboard/google/butterfly/smihandler.c M src/mainboard/google/parrot/smihandler.c M src/southbridge/intel/common/smihandler.c 4 files changed, 2 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/49249/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief0c3d36e6de6e18b7f2613f043ac4d31a193f9d Gerrit-Change-Number: 49249 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] cpu/x86/smm: Use common APMC logging
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49248 to look at the new patch set (#3). Change subject: [WIP] cpu/x86/smm: Use common APMC logging ...................................................................... [WIP] cpu/x86/smm: Use common APMC logging Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/smm/Makefile.inc M src/cpu/x86/smm/smi_trigger.c M src/include/cpu/x86/smm.h M src/mainboard/dell/optiplex_9010/smihandler.c M src/mainboard/google/butterfly/smihandler.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/lenovo/s230u/smihandler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 15 files changed, 34 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/49248/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Gerrit-Change-Number: 49248 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezzane: Add a minimal chipset tree
by Nico Huber (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49245 ) Change subject: soc/amd/cezzane: Add a minimal chipset tree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f Gerrit-Change-Number: 49245 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 10 Jan 2021 11:56:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Use wildcard for mb/smihandler.c
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49247 ) Change subject: arch/x86: Use wildcard for mb/smihandler.c ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49247/comment/cb645891_247a6052 PS1, Line 7: wildchar > wildcard Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481 Gerrit-Change-Number: 49247 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 11:49:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/autoport: Rename to mainboard_fill_gnvs()
by Nico Huber (Code Review) 10 Jan '21

10 Jan '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49231 ) Change subject: util/autoport: Rename to mainboard_fill_gnvs() ...................................................................... util/autoport: Rename to mainboard_fill_gnvs() Change-Id: Ia8d7083ca2f21abbb5f184c1b55dcf1bf047a7be Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49231 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M util/autoport/bd82x6x.go M util/autoport/readme.md 2 files changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 5d943e4..e2a84e4 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -359,10 +359,11 @@ defer gnvs.Close() Add_gpl(gnvs) - gnvs.WriteString(`#include <southbridge/intel/bd82x6x/nvs.h> + gnvs.WriteString(`#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> /* FIXME: check this function. */ -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default. */ gnvs->lids = 1; diff --git a/util/autoport/readme.md b/util/autoport/readme.md index bfaaef6..f2b2697 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -335,7 +335,7 @@ ## GNVS -`acpi_create_gnvs` sets values in GNVS, which then ACPI makes use of for +`mainboard_fill_gnvs` sets values in GNVS, which then ACPI makes use of for various power-related functions. Normally, there is no need to modify it on laptops (desktops have no "lid"!) but it makes sense to proofread it. -- To view, visit https://review.coreboot.org/c/coreboot/+/49231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8d7083ca2f21abbb5f184c1b55dcf1bf047a7be Gerrit-Change-Number: 49231 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: util/autoport: Rename to mainboard_fill_gnvs()
by Nico Huber (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Arthur Heymans, Kyösti Mälkki, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49231 ) Change subject: util/autoport: Rename to mainboard_fill_gnvs() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8d7083ca2f21abbb5f184c1b55dcf1bf047a7be Gerrit-Change-Number: 49231 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 11:41:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/braswell: Move board_id() to soc_fill_gnsvs()
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49003 ) Change subject: soc/intel/braswell: Move board_id() to soc_fill_gnsvs() ...................................................................... soc/intel/braswell: Move board_id() to soc_fill_gnsvs() Change-Id: I3d839333333b4762ae5350734c85471a3c12838a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/ramstage.c 2 files changed, 2 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/49003/1 diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index caeae39..520995a 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -75,6 +75,8 @@ gnvs->cid1 = wifi_regulatory_domain(); else gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; + + gnvs->bdid = board_id(); } int acpi_sci_irq(void) diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 68bddfb..d233778 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -2,7 +2,6 @@ #include <arch/cpu.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> @@ -15,7 +14,6 @@ #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/msr.h> -#include <soc/nvs.h> #include <soc/pattrs.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -136,14 +134,6 @@ return 1; } -static void set_board_id(void) -{ - struct global_nvs *gnvs = acpi_get_gnvs(); - if (!gnvs) - return; - gnvs->bdid = board_id(); -} - void soc_init_pre_device(struct soc_intel_braswell_config *config) { struct soc_gpio_config *gpio_config; @@ -157,7 +147,6 @@ intel_silicon_init(); set_max_freq(); - set_board_id(); /* Get GPIO initial states from mainboard */ gpio_config = mainboard_get_gpios(); setup_soc_gpios(gpio_config, config->enable_xdp_tap); -- To view, visit https://review.coreboot.org/c/coreboot/+/49003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d839333333b4762ae5350734c85471a3c12838a Gerrit-Change-Number: 49003 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ACPI: Add missing include in nvs.h
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49004 ) Change subject: ACPI: Add missing include in nvs.h ...................................................................... ACPI: Add missing include in nvs.h Change-Id: Ic779a668ebaa4f0c9bdef95fd6de8f0179e8a534 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/skylake/include/soc/nvs.h 6 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/49004/1 diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 45301c4..ab7021c 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -9,6 +9,7 @@ #ifndef _SOC_APOLLOLAKE_NVS_H_ #define _SOC_APOLLOLAKE_NVS_H_ +#include <stdint.h> #include <commonlib/helpers.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 41b827e..6eaf2c8 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -3,6 +3,7 @@ #ifndef _BAYTRAIL_NVS_H_ #define _BAYTRAIL_NVS_H_ +#include <stdint.h> #include <commonlib/helpers.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/device_nvs.h> diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index bc9b350..2184245 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -3,6 +3,7 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ +#include <stdint.h> #include <commonlib/helpers.h> #include <soc/device_nvs.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 4e2f3ea..2fe7bc8 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -3,6 +3,7 @@ #ifndef _BROADWELL_NVS_H_ #define _BROADWELL_NVS_H_ +#include <stdint.h> #include <commonlib/helpers.h> #include <soc/device_nvs.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index bb02cf5..38edfc7 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -3,6 +3,7 @@ #ifndef SOC_INTEL_COMMON_BLOCK_NVS_H #define SOC_INTEL_COMMON_BLOCK_NVS_H +#include <stdint.h> #include <commonlib/helpers.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index e1b99f2..3034276 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -3,6 +3,7 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ +#include <stdint.h> #include <commonlib/helpers.h> #include <vendorcode/google/chromeos/gnvs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/49004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic779a668ebaa4f0c9bdef95fd6de8f0179e8a534 Gerrit-Change-Number: 49004 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Rename to soc_fill_gnvs()
by Kyösti Mälkki (Code Review) 10 Jan '21

10 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48717 ) Change subject: soc/intel: Rename to soc_fill_gnvs() ...................................................................... soc/intel: Rename to soc_fill_gnvs() Replace acpi_create_gnvs() under soc/ to reflect their changed funcionality. Change-Id: I7bdbe0d6f795252e713e9785ada2b6320e6604b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c 11 files changed, 15 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/48717/1 diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index e188fa6..7eea4bf 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -279,7 +279,7 @@ return current; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 92d1daf..63787ed 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -72,7 +72,7 @@ return cstate_map; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { struct soc_intel_apollolake_config *cfg; cfg = config_of_soc(); diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 0a09cd4..b8fa9a7 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -181,7 +181,7 @@ return read32((void *)pmc_bar + IRQ_REG); } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { const struct soc_intel_cannonlake_config *config; config = config_of_soc(); diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 9dabcb8..b95ffcd 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -215,17 +215,15 @@ } #endif -__weak void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} - void southbridge_inject_dsdt(const struct device *device) { struct global_nvs *gnvs = acpi_get_gnvs(); if (!gnvs) return; - acpi_create_gnvs(gnvs); + soc_fill_gnvs(gnvs); + mainboard_fill_gnvs(gnvs); + acpi_inject_nvsa(); } diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 295a91a..82517d9 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -247,7 +247,7 @@ return current; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 565dc65..a9e56fa 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -177,7 +177,7 @@ return read32((void *)pmc_bar + IRQ_REG); } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 8494911..e480f55 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -273,7 +273,7 @@ return current; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 315e5f8..024fce3 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -155,7 +155,7 @@ return cores; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { const struct soc_intel_skylake_config *config = config_of_soc(); @@ -527,7 +527,7 @@ if (!gnvs) return; - acpi_create_gnvs(gnvs); + soc_fill_gnvs(gnvs); acpi_inject_nvsa(); } diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 7f15a96..69b7b17 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -273,7 +273,7 @@ return current; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 7c691b4..45b0ade 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -209,11 +209,8 @@ if (!gnvs) return; - /* FIXME: Implementations are asymmetrical. */ - if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) - acpi_create_gnvs(gnvs); - if (CONFIG(SOC_INTEL_SKYLAKE_SP)) - mainboard_fill_gnvs(); + soc_fill_gnvs(gnvs); + mainboard_fill_gnvs(); acpi_inject_nvsa(); } diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 8e73008..4808344 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -26,7 +26,7 @@ return current; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { /* CPU core count */ gnvs->pcnt = dev_count_cpu(); -- To view, visit https://review.coreboot.org/c/coreboot/+/48717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bdbe0d6f795252e713e9785ada2b6320e6604b9 Gerrit-Change-Number: 48717 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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