coreboot-gerrit January 2021

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Nico Huber (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Tim Crawford, Jeremy Soller, Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/a36a32df_5dc8cd62 PS7, Line 582: params->SiNumberOfSsidTableEntry = i; > Note that this approach will result in FSP programming the default SVID/SSID values when neither xHC […] Meh, you are right. It would be better to have only the lines that dereference the device node inside the if, e.g. ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID; ssid_table[i].device = PCI_SLOT(PCH_DEVFN_XHCI); ssid_table[i].function = PCI_FUNC(PCH_DEVFN_XHCI); dev = pcidev_path_on_root(PCH_DEVFN_XHCI); if (dev) { ssid_table[i].svid = dev->subsystem_vendor; ssid_table[i].ssid = dev->subsystem_device; } ++i; That would ensure that we always have the two entries, and if the devices are disabled, the entries shouldn't hurt. -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 23:49:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/intel/FSP2_0/CPX-SP: update to FSP ww01 release
by Angel Pons (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Marc Jones, Jonathan Zhang, Maxim Polyakov, Johnny Lin, Patrick Rudolph, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49246 ) Change subject: vc/intel/FSP2_0/CPX-SP: update to FSP ww01 release ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3242c8b50401757a28de8a9e9c71fb95bc0515dc Gerrit-Change-Number: 49246 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 23:35:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Angel Pons (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Tim Crawford, Nico Huber, Jeremy Soller. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 7: (3 comments) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/09b2269d_5601d398 PS6, Line 558: = {0} > Done Originally, this was non-static, which was wrong in its own way (see my reasoning on earlier patchsets), but required the initializer. File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/25dbf00f_68076ad6 PS7, Line 540: reserved1 You can omit the names for reserved fields. Personally, I'd also align the colons, but that's up to personal preference (coding style doesn't say anything about it) https://review.coreboot.org/c/coreboot/+/49104/comment/1466329c_e9c794bc PS7, Line 582: params->SiNumberOfSsidTableEntry = i; Note that this approach will result in FSP programming the default SVID/SSID values when neither xHCI nor HDA are present in the devicetree. This would be an extremely unlikely scenario, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 23:34:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA
by Clay Daniels (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Nico Huber, Felix Held. Clay Daniels has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49241 ) Change subject: superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Nico, this looks really good. I want to ask you later how you knew what to do. Thanks so much. -- To view, visit https://review.coreboot.org/c/coreboot/+/49241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3 Gerrit-Change-Number: 49241 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Clay Daniels <clay.daniels.jr(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Jan 2021 22:53:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Change __pci*|__pnp* device pointers to const
by Karthik Ramasubramanian (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Furquan Shaikh, Martin Roth. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49242 ) Change subject: util/sconfig: Change __pci*|__pnp* device pointers to const ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I061b05d994fc5c4156ee8bddabadf940f0aeeac3 Gerrit-Change-Number: 49242 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 22:37:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] pc80/rtc/option: Move register backup for SMI
by Kyösti Mälkki (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Alexander Couzens, Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49253 ) Change subject: [WIP] pc80/rtc/option: Move register backup for SMI ...................................................................... [WIP] pc80/rtc/option: Move register backup for SMI Change-Id: I025e9952a949834755f5cbc3dfe7b26ab9aaa032 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/lenovo/x60/smihandler.c M src/soc/intel/broadwell/pch/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 4 files changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/49253/1 diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index b5889db..a1b50b4 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -18,18 +18,11 @@ static void mainboard_smi_save_cmos(void) { u8 val; - u8 tmp70, tmp72; - - tmp70 = inb(0x70); - tmp72 = inb(0x72); val = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4); set_option("tft_brightness", &val); val = ec_read(H8_VOLUME_CONTROL); set_option("volume", &val); - - outb(tmp70, 0x70); - outb(tmp72, 0x72); } int mainboard_io_trap_handler(int smif) diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index 3a54749..abad5cd 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -128,14 +128,7 @@ static int power_on_after_fail(void) { u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - - /* save and recover RTC port values */ - u8 tmp70, tmp72; - tmp70 = inb(0x70); - tmp72 = inb(0x72); get_option(&s5pwr, "power_on_after_fail"); - outb(tmp70, 0x70); - outb(tmp72, 0x72); return (s5pwr == MAINBOARD_POWER_ON); } diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 90d2f7a..b5e4729 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -96,14 +96,7 @@ static int power_on_after_fail(void) { u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - - /* save and recover RTC port values */ - u8 tmp70, tmp72; - tmp70 = inb(0x70); - tmp72 = inb(0x72); get_option(&s5pwr, "power_on_after_fail"); - outb(tmp70, 0x70); - outb(tmp72, 0x72); return (s5pwr == MAINBOARD_POWER_ON); } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 948e216..03c39d9 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -79,14 +79,7 @@ static int power_on_after_fail(void) { u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - - /* save and recover RTC port values */ - u8 tmp70, tmp72; - tmp70 = inb(0x70); - tmp72 = inb(0x72); get_option(&s5pwr, "power_on_after_fail"); - outb(tmp70, 0x70); - outb(tmp72, 0x72); return (s5pwr == MAINBOARD_POWER_ON); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I025e9952a949834755f5cbc3dfe7b26ab9aaa032 Gerrit-Change-Number: 49253 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: ACPI: Add common FADT SMI entries
by Kyösti Mälkki (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Patrick Rudolph, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49252 ) Change subject: ACPI: Add common FADT SMI entries ...................................................................... ACPI: Add common FADT SMI entries Change-Id: I82d5a1423d08377759b58bfb7012d56198b00c9a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/skylake/fadt.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 18 files changed, 7 insertions(+), 114 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/49252/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 0ff0ded..e1ef978 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <cf9_reset.h> +#include <cpu/x86/smm.h> void arch_fill_fadt(acpi_fadt_t *fadt) { @@ -17,4 +18,10 @@ fadt->flags |= ACPI_FADT_RESET_REGISTER; } + + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } } diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index b89974b..4df4411 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -99,12 +99,6 @@ fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index e62f235..02dfd66 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -64,12 +64,6 @@ fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index f78188e..0420f31 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -13,12 +13,6 @@ fadt->sci_int = acpi_sci_irq(); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK; diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index f78188e..0420f31 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -13,12 +13,6 @@ fadt->sci_int = acpi_sci_irq(); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK; diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c index 8fbd0c4..0a8e0ff 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/soc/intel/broadwell/pch/fadt.c @@ -12,12 +12,6 @@ fadt->sci_int = acpi_sci_irq(); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm2_cnt_blk = pmbase + PM2_CNT; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 4a53c55..f679c46 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -125,12 +125,6 @@ fadt->sci_int = acpi_sci_irq(); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c index c8e4ec4..b92c4a3 100644 --- a/src/soc/intel/skylake/fadt.c +++ b/src/soc/intel/skylake/fadt.c @@ -15,12 +15,6 @@ fadt->sci_int = acpi_sci_irq(); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm2_cnt_blk = pmbase + PM2_CNT; diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index ee696ed..34a5912 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -28,12 +28,6 @@ fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ - if (permanent_smi_handler()) { - fadt->smi_cmd = ACPI_SMI_CTL_PORT; - fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; - fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; - } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 0bb9a97..4650a22 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -28,12 +28,6 @@ fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ - if (permanent_smi_handler()) { - fadt->smi_cmd = ACPI_SMI_CTL_PORT; - fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; - fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; - } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index b0f4777..285b108 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -15,12 +15,6 @@ fadt->sci_int = 0x9; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm2_cnt_blk = pmbase + PM2_CNT; diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 5aeff4e..77d2614 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -19,11 +19,6 @@ { fadt->sci_int = 9; - if (permanent_smi_handler()) { - /* TODO: SMI handler is not implemented. */ - fadt->smi_cmd = 0x00; - } - fadt->pm1a_evt_blk = DEFAULT_PMBASE; fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL; diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index 84ea73a..716088d 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -4,31 +4,12 @@ #include <acpi/acpi.h> #include <version.h> -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0x0 /* ACPI mode only */ -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x0 -#define ACPI_DISABLE 0xAA -#define ACPI_ENABLE 0x55 -#define S4_BIOS 0x77 -#define GNVS_UPDATE 0xea - void acpi_fill_fadt(acpi_fadt_t *fadt) { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; fadt->sci_int = 0x9; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->pstate_cnt = PST_CONTROL; - } - fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + 0x4; fadt->pm_tmr_blk = pmbase + 0x8; diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 153ddea..7dde495 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -16,12 +16,6 @@ fadt->sci_int = 0x9; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm2_cnt_blk = pmbase + PM2_CNT; diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c index 8a48f1b..fea2e1c 100644 --- a/src/southbridge/intel/i82801ix/fadt.c +++ b/src/southbridge/intel/i82801ix/fadt.c @@ -12,12 +12,6 @@ fadt->sci_int = 0x9; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm2_cnt_blk = pmbase + PM2_CNT; diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index 377b4d2..f18970c 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -12,12 +12,6 @@ fadt->sci_int = 0x9; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm2_cnt_blk = pmbase + PM2_CNT; diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index ccd9f57..af244d1 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -15,12 +15,6 @@ fadt->sci_int = 0x9; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm2_cnt_blk = pmbase + PM2_CNT; diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index dee0601..b216bc7 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -14,12 +14,6 @@ fadt->sci_int = 0x9; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm2_cnt_blk = pmbase + PM2_CNT; -- To view, visit https://review.coreboot.org/c/coreboot/+/49252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82d5a1423d08377759b58bfb7012d56198b00c9a Gerrit-Change-Number: 49252 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: sb,soc/intel: Refactor power_on_after_fail option
by Kyösti Mälkki (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49251 ) Change subject: sb,soc/intel: Refactor power_on_after_fail option ...................................................................... sb,soc/intel: Refactor power_on_after_fail option It's only necessary to call get_option() with SLP_TYP S5. Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/pch/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 3 files changed, 40 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/49251/1 diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index c6632da..3a54749 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -125,13 +125,9 @@ printk(BIOS_INFO, "Backlight turned off\n"); } -static void southbridge_smi_sleep(void) +static int power_on_after_fail(void) { - u8 reg8; - u32 reg32; - u8 slp_typ; u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - u16 pmbase = get_pmbase(); /* save and recover RTC port values */ u8 tmp70, tmp72; @@ -140,6 +136,15 @@ get_option(&s5pwr, "power_on_after_fail"); outb(tmp70, 0x70); outb(tmp72, 0x72); + return (s5pwr == MAINBOARD_POWER_ON); +} + +static void southbridge_smi_sleep(void) +{ + u8 reg8; + u32 reg32; + u8 slp_typ; + u16 pmbase = get_pmbase(); /* First, disable further SMIs */ disable_smi(SLP_SMI_EN); @@ -193,12 +198,10 @@ /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pci_read_config8(PCH_DEV_LPC, GEN_PMCON_3); - if (s5pwr == MAINBOARD_POWER_ON) - reg8 &= ~1; + if (power_on_after_fail()) + pci_and_config8(PCH_DEV_LPC, GEN_PMCON_3, ~1); else - reg8 |= 1; - pci_write_config8(PCH_DEV_LPC, GEN_PMCON_3, reg8); + pci_or_config8(PCH_DEV_LPC, GEN_PMCON_3, 1); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 18f171d..90d2f7a 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -93,20 +93,25 @@ { } -static void southbridge_smi_sleep(void) +static int power_on_after_fail(void) { - u8 reg8; - u32 reg32; - u8 slp_typ; u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - // save and recover RTC port values + /* save and recover RTC port values */ u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); get_option(&s5pwr, "power_on_after_fail"); outb(tmp70, 0x70); outb(tmp72, 0x72); + return (s5pwr == MAINBOARD_POWER_ON); +} + +static void southbridge_smi_sleep(void) +{ + u8 reg8; + u32 reg32; + u8 slp_typ; /* First, disable further SMIs */ write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) & ~SLP_SMI_EN); @@ -156,13 +161,10 @@ /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3); - if (s5pwr == MAINBOARD_POWER_ON) { - reg8 &= ~1; - } else { - reg8 |= 1; - } - pci_write_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, reg8); + if (power_on_after_fail()) + pci_and_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, ~1); + else + pci_or_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, 1); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 5e31808..948e216 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -76,13 +76,9 @@ } } -static void southbridge_smi_sleep(void) +static int power_on_after_fail(void) { - u8 reg8; - u32 reg32; - u8 slp_typ; u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - u16 pmbase = get_pmbase(); /* save and recover RTC port values */ u8 tmp70, tmp72; @@ -91,6 +87,15 @@ get_option(&s5pwr, "power_on_after_fail"); outb(tmp70, 0x70); outb(tmp72, 0x72); + return (s5pwr == MAINBOARD_POWER_ON); +} + +static void southbridge_smi_sleep(void) +{ + u8 reg8; + u32 reg32; + u8 slp_typ; + u16 pmbase = get_pmbase(); /* First, disable further SMIs */ disable_smi(SLP_SMI_EN); @@ -142,12 +147,10 @@ /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); - if (s5pwr == MAINBOARD_POWER_ON) - reg8 &= ~1; + if (power_on_after_fail()) + pci_and_config8(PCH_DEV_LPC, GEN_PMCON_3, ~1); else - reg8 |= 1; - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); + pci_or_config8(PCH_DEV_LPC, GEN_PMCON_3, 1); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); -- To view, visit https://review.coreboot.org/c/coreboot/+/49251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce Gerrit-Change-Number: 49251 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: sb,soc/intel: Remove no-op APMC for C-state and P-state
by Kyösti Mälkki (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49250 ) Change subject: sb,soc/intel: Remove no-op APMC for C-state and P-state ...................................................................... sb,soc/intel: Remove no-op APMC for C-state and P-state Change-Id: I3c1aa7f68eb03f04ddb9c1a5e960e3e2050a029c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/lynxpoint/smihandler.c 11 files changed, 0 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/49250/1 diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 1a33444..41eeeda 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -283,20 +283,6 @@ reg8 = apm_get_apmc(); switch (reg8) { - case APM_CNT_CST_CONTROL: - /* - * Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; - case APM_CNT_PST_CONTROL: - /* - * Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; case APM_CNT_ACPI_DISABLE: disable_pm1_control(SCI_EN); break; diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 7343d47..138dc33 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -262,20 +262,6 @@ reg8 = apm_get_apmc(); switch (reg8) { - case APM_CNT_CST_CONTROL: - /* - * Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; - case APM_CNT_PST_CONTROL: - /* - * Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; case APM_CNT_ACPI_DISABLE: disable_pm1_control(SCI_EN); break; diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index 02c795e..c6632da 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -314,10 +314,6 @@ reg8 = apm_get_apmc(); switch (reg8) { - case APM_CNT_CST_CONTROL: - break; - case APM_CNT_PST_CONTROL: - break; case APM_CNT_ACPI_DISABLE: disable_pm1_control(SCI_EN); break; diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 79605ce..e29e3b5 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -336,20 +336,6 @@ apmc_log(__func__, reg8); switch (reg8) { - case APM_CNT_CST_CONTROL: - /* - * Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; - case APM_CNT_PST_CONTROL: - /* - * Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; case APM_CNT_ACPI_DISABLE: pmc_disable_pm1_control(SCI_EN); break; diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index f00d921..68e8519 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -222,18 +222,6 @@ reg8 = apm_get_apmc(); switch (reg8) { - case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; - case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; case APM_CNT_ACPI_DISABLE: disable_pm1_control(SCI_EN); break; diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 07cd662..18f171d 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -277,18 +277,6 @@ reg8 = apm_get_apmc(); switch (reg8) { - case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; - case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; case APM_CNT_ACPI_DISABLE: write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) & ~SCI_EN); break; diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index bb50eaa..0d3b843 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -299,18 +299,6 @@ reg8 = apm_get_apmc(); switch (reg8) { - case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; - case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; case APM_CNT_ACPI_DISABLE: pmctrl = inl(pmbase + PM1_CNT); pmctrl &= ~SCI_EN; diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 3be40b9..153ddea 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -20,8 +20,6 @@ fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; - fadt->cst_cnt = APM_CNT_CST_CONTROL; } fadt->pm1a_evt_blk = pmbase; diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c index b7da216..8a48f1b 100644 --- a/src/southbridge/intel/i82801ix/fadt.c +++ b/src/southbridge/intel/i82801ix/fadt.c @@ -16,8 +16,6 @@ fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; - fadt->cst_cnt = APM_CNT_CST_CONTROL; } fadt->pm1a_evt_blk = pmbase; diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index fd55661..377b4d2 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -16,8 +16,6 @@ fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; - fadt->cst_cnt = APM_CNT_CST_CONTROL; } fadt->pm1a_evt_blk = pmbase; diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index c923f68..5e31808 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -277,18 +277,6 @@ chipset_finalized = 1; break; - case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; - case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - break; case APM_CNT_ACPI_DISABLE: disable_pm1_control(SCI_EN); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/49250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c1aa7f68eb03f04ddb9c1a5e960e3e2050a029c Gerrit-Change-Number: 49250 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Change some SMI logging
by Kyösti Mälkki (Code Review) 08 Jan '21

08 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49249 ) Change subject: sb/intel/common: Change some SMI logging ...................................................................... sb/intel/common: Change some SMI logging Change-Id: Ief0c3d36e6de6e18b7f2613f043ac4d31a193f9d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/dell/optiplex_9010/smihandler.c M src/mainboard/google/butterfly/smihandler.c M src/mainboard/google/parrot/smihandler.c M src/southbridge/intel/common/smihandler.c 4 files changed, 2 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/49249/1 diff --git a/src/mainboard/dell/optiplex_9010/smihandler.c b/src/mainboard/dell/optiplex_9010/smihandler.c index f3ba57c..1c7d328 100644 --- a/src/mainboard/dell/optiplex_9010/smihandler.c +++ b/src/mainboard/dell/optiplex_9010/smihandler.c @@ -6,11 +6,6 @@ #include <cpu/x86/smm.h> #include <superio/smsc/sch5545/sch5545.h> -void mainboard_smi_gpi(u32 gpi_sts) -{ - printk(BIOS_SPEW, "%s: gpi_sts: %08x\n", __func__, gpi_sts); -} - int mainboard_smi_apmc(u8 data) { u8 val; @@ -38,8 +33,3 @@ } return 0; } - -void mainboard_smi_sleep(u8 slp_typ) -{ - printk(BIOS_SPEW, "%s: SMI sleep: %02x\n", __func__, slp_typ); -} diff --git a/src/mainboard/google/butterfly/smihandler.c b/src/mainboard/google/butterfly/smihandler.c index 0ffa0e6..ac38790 100644 --- a/src/mainboard/google/butterfly/smihandler.c +++ b/src/mainboard/google/butterfly/smihandler.c @@ -13,15 +13,8 @@ #include <ec/quanta/ene_kb3940q/ec.h> #include "ec.h" -void mainboard_smi_gpi(u32 gpi_sts) -{ - printk(BIOS_DEBUG, "warn: unknown mainboard_smi_gpi: %x\n", gpi_sts); -} - void mainboard_smi_sleep(u8 slp_typ) { - printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ); - /* Tell the EC to Enable USB power for S3 if requested */ if (gnvs->s3u0 != 0 || gnvs->s3u1 != 0) ec_mem_write(EC_EC_PSW, ec_mem_read(EC_EC_PSW) | EC_PSW_USB); diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 89d4cac..9b53bc4 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -36,7 +36,6 @@ void mainboard_smi_gpi(u32 gpi_sts) { - printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts); if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending events from EC */ while (mainboard_smi_ec() != EC_NO_EVENT); @@ -51,7 +50,6 @@ void mainboard_smi_sleep(u8 slp_typ) { - printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ); /* Disable SCI and SMI events */ /* Clear pending events that may trigger immediate wake */ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7256497..07cd662 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -113,9 +113,10 @@ /* Figure out SLP_TYP */ reg32 = read_pmbase32(PM1_CNT); - printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); + printk(BIOS_SPEW, "SMI#: SLP = 0x%08x, TYPE = 0x%02x\n", reg32, slp_typ); + southbridge_smm_xhci_sleep(slp_typ); /* Do any mainboard sleep handling */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief0c3d36e6de6e18b7f2613f043ac4d31a193f9d Gerrit-Change-Number: 49249 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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