John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49202 )
Change subject: mb/google/volteer: Configure Delbin USB2 ports for Type C ......................................................................
mb/google/volteer: Configure Delbin USB2 ports for Type C
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU to recover a USB3 device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892 TEST=Booted to kernel on Delbin board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/49202/1
diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 5774047..aa06d09 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -51,7 +51,9 @@ .tx_emp_enable = USB2_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_56P3MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + .type_c = 1, }" + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
# Acoustic settings register "AcousticNoiseMitigation" = "1"
Hello build bot (Jenkins), Chiranjeevi Rapolu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49202
to look at the new patch set (#3).
Change subject: mb/google/volteer: Configure Delbin USB2 ports for Type C ......................................................................
mb/google/volteer: Configure Delbin USB2 ports for Type C
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU to recover a USB3 device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892 TEST=Booted to kernel on Delbin board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/49202/3
Attention is currently required from: John Zhao, Duncan Laurie. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49202 )
Change subject: mb/google/volteer: Configure Delbin USB2 ports for Type C ......................................................................
Patch Set 3: Code-Review+2
Attention is currently required from: John Zhao, Duncan Laurie. Chiranjeevi Rapolu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49202 )
Change subject: mb/google/volteer: Configure Delbin USB2 ports for Type C ......................................................................
Patch Set 3: Code-Review+1
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49202 )
Change subject: mb/google/volteer: Configure Delbin USB2 ports for Type C ......................................................................
mb/google/volteer: Configure Delbin USB2 ports for Type C
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU to recover a USB3 device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892 TEST=Booted to kernel on Delbin board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49202 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Chiranjeevi Rapolu chiranjeevi.rapolu@intel.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Chiranjeevi Rapolu: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 5774047..aa06d09 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -51,7 +51,9 @@ .tx_emp_enable = USB2_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_56P3MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + .type_c = 1, }" + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
# Acoustic settings register "AcousticNoiseMitigation" = "1"
-
Chiranjeevi Rapolu (Code Review) -
John Zhao (Code Review)
-
Tim Wawrzynczak (Code Review)