Change in coreboot[master]: mb/asrock/h110m: Fix HECI state in devicetree

[Felix Singer (Code Review)]

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49184 )

Change subject: mb/asrock/h110m: Fix HECI state in devicetree
......................................................................

mb/asrock/h110m: Fix HECI state in devicetree

Disable HECI in devicetree making its state equal with the HeciEnabled
option.

Change-Id: I67a9f0a66bcc51c6153a76bfaaebdf1e7f07d55d
Signed-off-by: Felix Singer 
---
M src/mainboard/asrock/h110m/devicetree.cb
1 file changed, 1 insertion(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/49184/1

diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 909c050..ffa35f7 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -187,10 +187,8 @@
    	device pci 15.1 off end # I2C #1
    	device pci 15.2 off end # I2C #2
    	device pci 15.3 off end # I2C #3
-		device pci 16.0 on      # Management Engine Interface 1
+		device pci 16.0 off     # Management Engine Interface 1
    		subsystemid 0x1849 0xa131
-
-			# FIXME: does not match devicetree!
    		register "HeciEnabled" = "0"
    	end
    	device pci 16.1 off end # Management Engine Interface 2

[Felix Singer (Code Review)]

Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/49184 )

Change subject: mb/asrock/h110m: Fix HECI state in devicetree
......................................................................

mb/asrock/h110m: Fix HECI state in devicetree

Disable HECI in devicetree making its state equal with the HeciEnabled
option.

Change-Id: I67a9f0a66bcc51c6153a76bfaaebdf1e7f07d55d
Signed-off-by: Felix Singer 
---
M src/mainboard/asrock/h110m/devicetree.cb
1 file changed, 1 insertion(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/49184/2

[Nico Huber (Code Review)]

Attention is currently required from:  Felix Singer.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49184 )

Change subject: mb/asrock/h110m: Fix HECI state in devicetree
......................................................................

Patch Set 3:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/49184/comment/3b183ef1_cb3698c3 
PS3, Line 9: making its state equal with the HeciEnabled
           : option
Should we? It depends on the point in coreboot when `HeciEnabled`
is committed. If that happens before PCI enumeration, the devicetree
should match (otherwise we'd get a warning about 16.0, easy to check).
But if it happens later, different values could still be meaningful.

[Felix Singer (Code Review)]

Attention is currently required from:  Felix Singer.
Hello build bot (Jenkins), Maxim Polyakov,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/49184

to look at the new patch set (#4).

Change subject: mb/asrock/h110m: Fix HECI state in devicetree
......................................................................

mb/asrock/h110m: Fix HECI state in devicetree

Disable HECI in devicetree making its state equal with the HeciEnabled
option.

Change-Id: I67a9f0a66bcc51c6153a76bfaaebdf1e7f07d55d
Signed-off-by: Felix Singer 
---
M src/mainboard/asrock/h110m/devicetree.cb
1 file changed, 1 insertion(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/49184/4

[Felix Singer (Code Review)]

Attention is currently required from: Nico Huber.
 Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49184 )

Change subject: mb/asrock/h110m: Fix HECI state in devicetree
......................................................................

Patch Set 5: Code-Review-1

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/49184/comment/375991d4_ba90857c 
PS3, Line 9: making its state equal with the HeciEnabled
           : option
> Should we? It depends on the point in coreboot when `HeciEnabled` […]

Just looked it after. It happens while `soc_finalize()`, after PCI enumeration. I thought `HeciEnabled` would set a FSP UPD. So I will leave it as it is.

[Nico Huber (Code Review)]

Attention is currently required from:  Felix Singer.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49184 )

Change subject: mb/asrock/h110m: Fix HECI state in devicetree
......................................................................

Patch Set 5:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/49184/comment/7f126a22_74d2c235 
PS3, Line 9: making its state equal with the HeciEnabled
           : option
> Just looked it after. It happens while `soc_finalize()`, after PCI enumeration. […]

Maybe just rename and invert `HeciEnabled` --> `HideHeci`?

[Felix Singer (Code Review)]

Attention is currently required from: Nico Huber.
 Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49184 )

Change subject: mb/asrock/h110m: Fix HECI state in devicetree
......................................................................

Patch Set 5:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/49184/comment/9f3b05a8_13c1e3cd 
PS3, Line 9: making its state equal with the HeciEnabled
           : option
> Maybe just rename and invert `HeciEnabled` --> `HideHeci`?

I had the same idea, since its name might be too confusing, but I will do that in a seperate patch.

[Felix Singer (Code Review)]

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49184 )

Change subject: mb/asrock/h110m: Fix HECI state in devicetree
......................................................................

Abandoned