Attention is currently required from: Nico Huber, Jeremy Soller, Angel Pons. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 )
Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ......................................................................
Patch Set 6:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49104/comment/384f3082_6189bc00 PS5, Line 14: the TigerLake FSP Integration Guide.
I will clarify the it to be the table override behavior in the message, and reference the section in […]
Done
https://review.coreboot.org/c/coreboot/+/49104/comment/d990bb8c_16489ca9 PS5, Line 23: Tested by checking lspci output on System76 galp3-c, oryp5, oryp6.
These are WHL (galp3-c), CFL (oryp5, CB:47892), and CML (oryp6, CB:47768). […]
Done
File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/49104/comment/29a8388b_7c6d80c5 PS5, Line 552: 0
No, what Nico means is that the resulting value of `segbusdevfuncregister` makes FSP try to rewrite […]
Ack
https://review.coreboot.org/c/coreboot/+/49104/comment/6ca257f9_c870f9ed PS5, Line 561: dev = pcidev_path_on_root(PCH_DEVFN_XHCI); : if (dev) : pci_dev_set_subsystem(dev, dev->subsystem_vendor, : dev->subsystem_device); : : dev = pcidev_path_on_root(PCH_DEVFN_HDA); : if (dev) : pci_dev_set_subsystem(dev, dev->subsystem_vendor, : dev->subsystem_device);
Yes. Based on your other comments, I believe this is the better option. […]
Done