coreboot-gerrit January 2021

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Change in coreboot[master]: mb/asrock/h110m: Drop DEVICETREE from Kconfig
by Felix Singer (Code Review) 08 Jan '21

08 Jan '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49183 ) Change subject: mb/asrock/h110m: Drop DEVICETREE from Kconfig ...................................................................... mb/asrock/h110m: Drop DEVICETREE from Kconfig Drop DEVICETREE from Kconfig since its value is the default. Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Change-Id: Idbcd49cca6494ae2da0f364c24638d7ca11911da Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/asrock/h110m/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/49183/1 diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index d923c30..c4b48c3 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -33,10 +33,6 @@ int default 8 -config DEVICETREE - string - default "devicetree.cb" - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xd00 -- To view, visit https://review.coreboot.org/c/coreboot/+/49183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbcd49cca6494ae2da0f364c24638d7ca11911da Gerrit-Change-Number: 49183 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/clevo/cml-u: Drop VGA_BIOS_FILE from Kconfig
by Felix Singer (Code Review) 08 Jan '21

08 Jan '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49138 ) Change subject: mb/clevo/cml-u: Drop VGA_BIOS_FILE from Kconfig ...................................................................... mb/clevo/cml-u: Drop VGA_BIOS_FILE from Kconfig It doesn't make sense to configure that filename in Kconfig, since the filename can be changed either and is chosen by the user. So remove it. Change-Id: I3eed05637da29096bc1d134505d7335db5db1439 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/49138/1 diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index f8bf1ba..5653fb4 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -66,10 +66,6 @@ int default 512 -config VGA_BIOS_FILE - string - default "pci8086,9b41.rom" - config VGA_BIOS_ID string default "8086,9b41" -- To view, visit https://review.coreboot.org/c/coreboot/+/49138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3eed05637da29096bc1d134505d7335db5db1439 Gerrit-Change-Number: 49138 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: ec/google/chromeec: add SSFC CBI support
by Marco Chen (Code Review) 08 Jan '21

08 Jan '21

Marco Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48791 ) Change subject: ec/google/chromeec: add SSFC CBI support ...................................................................... ec/google/chromeec: add SSFC CBI support An API is added to get SSFC value from cros EC. BUG=b:174118027 BRANCH=octopus TEST=check SSFC value from EC is correct compared to value in CBI Change-Id: Ifd521514bbc2e90c789f3760b72e8326e614e2b1 --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/48791/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index ed7f97d..fdbe582 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -863,6 +863,11 @@ return cbi_get_uint32(version, CBI_TAG_BOARD_VERSION); } +int google_chromeec_cbi_get_ssfc(uint32_t *ssfc) +{ + return cbi_get_uint32(ssfc, CBI_TAG_SSFC); +} + static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag) { struct ec_params_get_cbi params = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index c3c456f..7c41f04 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -89,6 +89,7 @@ /* version may be stored in CBI as a smaller integer width, but the EC code handles it correctly. */ int google_chromeec_cbi_get_board_version(uint32_t *version); +int google_chromeec_cbi_get_ssfc(uint32_t *ssfc); #define CROS_SKU_UNKNOWN 0xFFFFFFFF #define CROS_SKU_UNPROVISIONED 0x7FFFFFFF -- To view, visit https://review.coreboot.org/c/coreboot/+/48791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd521514bbc2e90c789f3760b72e8326e614e2b1 Gerrit-Change-Number: 48791 Gerrit-PatchSet: 1 Gerrit-Owner: Marco Chen <marcochen(a)google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/common/uart: Restrict scope of uart_common_init to uart.c
by Furquan Shaikh (Code Review) 08 Jan '21

08 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49211 ) Change subject: soc/intel/common/uart: Restrict scope of uart_common_init to uart.c ...................................................................... soc/intel/common/uart: Restrict scope of uart_common_init to uart.c uart_common_init is not used outside of soc/intel/common/block/uart.c. This change restricts the scope to this file and drops the declaration from uart.h Change-Id: I499a53506f9b2e91ecc7334bf9b023d342e802fc Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/uart.c 2 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/49211/1 diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index 87fdf68..fd65f4c 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -24,12 +24,6 @@ */ /* - * Common routine to initialize UART controller PCI config space, take it out of - * reset and configure M/N dividers. - */ -void uart_common_init(const struct device *dev, uintptr_t baseaddr); - -/* * Check if UART debug controller is initialized * Returns: * true = If debug controller PCI config space is initialized and device is diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 75c16d4..1e205ef 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -58,7 +58,7 @@ return UART_CONSOLE_INVALID_INDEX; } -void uart_common_init(const struct device *device, uintptr_t baseaddr) +static void uart_common_init(const struct device *device, uintptr_t baseaddr) { #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCI_BDF(device); -- To view, visit https://review.coreboot.org/c/coreboot/+/49211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I499a53506f9b2e91ecc7334bf9b023d342e802fc Gerrit-Change-Number: 49211 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: soc/intel/common: Pass in pci_devfn_t into lpss_set_power
by Furquan Shaikh (Code Review) 08 Jan '21

08 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49210 ) Change subject: soc/intel/common: Pass in pci_devfn_t into lpss_set_power ...................................................................... soc/intel/common: Pass in pci_devfn_t into lpss_set_power This change updates the parameter passed into `lpss_set_power()` from struct device * to pci_devfn_t. This allows the users in the early stages to use pci_devfn_t instead of having to walk the device tree to get a pointer to the relevant device structure. It is important for optimizing out unnecessary components of the device tree from the early stages. Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/lpss.h M src/soc/intel/common/block/lpss/lpss.c M src/soc/intel/common/block/uart/uart.c 5 files changed, 10 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/49210/1 diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 8363713..395a14d 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -448,7 +448,6 @@ int devfn; uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol; struct gspi_ctrlr_params params, *p = &params; - const struct device *device; /* Only chip select 0 is supported. */ if (dev->cs != 0) { @@ -468,14 +467,9 @@ } devfn = gspi_soc_bus_to_devfn(p->gspi_bus); - /* - * devfn is already validated as part of gspi_ctrlr_params_init. - * No need to revalidate it again. - */ - device = pcidev_path_on_root(devfn); /* Ensure controller is in D0 state */ - lpss_set_power_state(device, STATE_D0); + lpss_set_power_state(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)), STATE_D0); /* Take controller out of reset, keeping DMA in reset. */ gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET); diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 5aa7729..57e5d5e 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -38,7 +38,6 @@ static int lpss_i2c_early_init_bus(unsigned int bus) { const struct dw_i2c_bus_config *config; - const struct device *tree_dev; pci_devfn_t dev; int devfn; uintptr_t base; @@ -52,11 +51,6 @@ /* Look up the controller device in the devicetree */ dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - tree_dev = pcidev_path_on_root(devfn); - if (!tree_dev || !tree_dev->enabled) { - printk(BIOS_ERR, "I2C%u device not enabled\n", bus); - return -1; - } /* Skip if not enabled for early init */ config = dw_i2c_get_soc_cfg(bus); @@ -75,7 +69,7 @@ lpss_reset_release(base); /* Ensure controller is in D0 state */ - lpss_set_power_state(tree_dev, STATE_D0); + lpss_set_power_state(dev, STATE_D0); /* Initialize the controller */ if (dw_i2c_init(bus, config) < 0) { @@ -153,7 +147,7 @@ return; /* Ensure controller is in D0 state */ - lpss_set_power_state(dev, STATE_D0); + lpss_set_power_state(PCI_BDF(dev), STATE_D0); /* Take device out of reset if its not done before */ if (lpss_is_controller_in_reset(base_address)) diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index 145857c..8d22e7a 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -25,7 +25,7 @@ bool lpss_is_controller_in_reset(uintptr_t base); /* Set controller power state to D0 or D3*/ -void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state); +void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state); /* * Handler to get list of LPSS controllers. The SOC is expected to send out a diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 74c7aa1..6e33c0f 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -65,16 +65,12 @@ } /* Set controller power state to D0 or D3 */ -void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state) +void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state) { -#if defined(__SIMPLE_DEVICE__) - unsigned int devfn = dev->path.pci.devfn; - pci_devfn_t lpss_dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); -#else - const struct device *lpss_dev = dev; -#endif - - pci_update_config8(lpss_dev, PME_CTRL_STATUS, ~POWER_STATE_MASK, state); + uint8_t reg8 = pci_s_read_config8(devfn, PME_CTRL_STATUS); + reg8 &= ~POWER_STATE_MASK; + reg8 |= state; + pci_s_write_config8(devfn, PME_CTRL_STATUS, reg8); } bool is_dev_lpss(const struct device *dev) diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 142a936..75c16d4 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -26,7 +26,7 @@ static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr) { /* Ensure controller is in D0 state */ - lpss_set_power_state(dev, STATE_D0); + lpss_set_power_state(PCI_BDF(dev), STATE_D0); /* Take UART out of reset */ lpss_reset_release(baseaddr); -- To view, visit https://review.coreboot.org/c/coreboot/+/49210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f Gerrit-Change-Number: 49210 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range()
by Furquan Shaikh (Code Review) 08 Jan '21

08 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49209 ) Change subject: soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range() ...................................................................... soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range() This change drops the parameter `struct device *dev` from the function `soc_get_gen_io_dec_range()`. This function uses the parameter dev to get a pointer to config structure for extracting the decode ranges configured by mainboard in device tree. However, there is no separate chip driver for the LPC device which means that the SoC code can use `config_of_soc()` to get to SoC chip config instead of using the LPC device. This change is being done in preparation to clean up the device tree/chip config access in early stages that allows for optimizing the inclusion of device tree elements in the early stages. Change-Id: I3ea53ddc771f592dd0ea5e5e809be2d2eff7f16d Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/alderlake/espi.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/lpc.c 10 files changed, 18 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/49209/1 diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index c909030..b237727 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -35,9 +35,9 @@ return lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index b21c117..c8e35c4 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -33,9 +33,9 @@ return cnl_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 2fdcdef..82cba8e 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -98,8 +98,7 @@ /* Enable PCH LPC by setting up generic decode range registers. */ void pch_enable_lpc(void); /* Get SoC's generic IO decoder range register settings. */ -void soc_get_gen_io_dec_range(const struct device *dev, - uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); /* Mirror generic IO decoder range register settings into DMI PCR. */ void soc_setup_dmi_pcr_io_dec(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); /* Add resource into LPC PCI device space */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 67dd661..d050ee3 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -270,15 +270,9 @@ void pch_enable_lpc(void) { - /* Lookup device tree in romstage */ - const struct device *dev; uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]; - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); - if (!dev) - return; - - soc_get_gen_io_dec_range(dev, gen_io_dec); + soc_get_gen_io_dec_range(gen_io_dec); lpc_set_gen_decode_range(gen_io_dec); soc_setup_dmi_pcr_io_dec(gen_io_dec); if (ENV_PAYLOAD_LOADER) diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index a531fcc..8f82755 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -31,9 +31,9 @@ return ehl_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 7f9ff2f..4107d7e 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -32,9 +32,9 @@ return icl_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index 0977857..11299a9 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -32,9 +32,9 @@ return jsl_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index f9c6639..b83fadd 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -29,9 +29,9 @@ return skl_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index acd3b12..8602b0d 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -38,9 +38,9 @@ return tgl_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 3169545..dee99b7 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -18,9 +18,9 @@ return xeon_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; -- To view, visit https://review.coreboot.org/c/coreboot/+/49209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ea53ddc771f592dd0ea5e5e809be2d2eff7f16d Gerrit-Change-Number: 49209 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: cpu/x86/smm: Use append instead of assign for smm-c-deps
by Furquan Shaikh (Code Review) 08 Jan '21

08 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49208 ) Change subject: cpu/x86/smm: Use append instead of assign for smm-c-deps ...................................................................... cpu/x86/smm: Use append instead of assign for smm-c-deps This change uses append operation (+=) instead of assignment (:=) for smm-c-deps to ensure that any earlier assignment is not overwritten. Change-Id: Ic1d62b414cfe3f61ee2b80b026b7338faa186904 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/cpu/x86/smm/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/49208/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index eb386a6..1ed018d 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -17,7 +17,7 @@ smmstub-generic-ccopts += -D__SMM__ smm-generic-ccopts += -D__SMM__ -smm-c-deps:=$$(OPTION_TABLE_H) +smm-c-deps+=$$(OPTION_TABLE_H) $(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(filter-out %.ld, $(smm-objs)) --no-whole-archive $(COMPILER_RT_smm) --end-group -- To view, visit https://review.coreboot.org/c/coreboot/+/49208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1d62b414cfe3f61ee2b80b026b7338faa186904 Gerrit-Change-Number: 49208 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

6 6

Change in coreboot[master]: soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports
by John Zhao (Code Review) 08 Jan '21

08 Jan '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49052 ) Change subject: soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports ...................................................................... soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI USB2 port reset event issued by the xHCI driver shall trigger a message upstream to CPU to wake it from the low power state which allows a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Built and booted to kernel on Voxel board. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f --- M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/usb.h 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/49052/1 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index ed34897..295f789 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -159,6 +159,9 @@ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; else params->Usb2OverCurrentPin[i] = 0xff; + + if (config->usb2_ports[i].type_c) + params->PortResetMessageEnable[i] = 1; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { diff --git a/src/soc/intel/tigerlake/include/soc/usb.h b/src/soc/intel/tigerlake/include/soc/usb.h index 69b5ca8..5dea4bf 100644 --- a/src/soc/intel/tigerlake/include/soc/usb.h +++ b/src/soc/intel/tigerlake/include/soc/usb.h @@ -31,6 +31,7 @@ uint8_t tx_emp_enable; uint8_t pre_emp_bias; uint8_t pre_emp_bit; + uint8_t type_c; }; /* USB Overcurrent pins definition */ @@ -112,6 +113,7 @@ .tx_emp_enable = USB2_PRE_EMP_ON, \ .pre_emp_bias = USB2_BIAS_56P3MV, \ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + .type_c = 1, \ } struct usb3_port_config { -- To view, visit https://review.coreboot.org/c/coreboot/+/49052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f Gerrit-Change-Number: 49052 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: util/testing: remove genprof target
by Patrick Georgi (Code Review) 08 Jan '21

08 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49226 ) Change subject: util/testing: remove genprof target ...................................................................... util/testing: remove genprof target commit 8c99c27df10f6c5a120e41ffb0948e357f5a2d20 removed util/genprof, so it needs to be dropped here as well to avoid spurious breakages of the build. Change-Id: I420b5c43e2d97373a8e665f457463a06e16ecfb9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49226 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/testing/Makefile.inc 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index da6db60..c530fa8 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -55,7 +55,6 @@ cbmem \ ectool \ futility \ -genprof \ intelmetool \ inteltool \ intelvbttool \ -- To view, visit https://review.coreboot.org/c/coreboot/+/49226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I420b5c43e2d97373a8e665f457463a06e16ecfb9 Gerrit-Change-Number: 49226 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: ec/google/chromeec: Check AP reset cause for watchdog reset
by Yu-Ping Wu (Code Review) 08 Jan '21

08 Jan '21

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49113 ) Change subject: ec/google/chromeec: Check AP reset cause for watchdog reset ...................................................................... ec/google/chromeec: Check AP reset cause for watchdog reset Different from mt8183, mt8192 doesn't need to trigger EC reboot on HW initiated watchdog reset. Therefore, ec_reset_flags cannot be used to determine AP watchdog reset. Instead we check the cause of the last AP reset. To expose AP reset causes, CL:2607150 adds enum chipset_reset_reason to ec_commands.h. This CL also synchronizes it from the Chromium EC repository. BUG=b:174443398 TEST=emerge-asurada coreboot TEST=crash.WatchdogCrash passed on asurada BRANCH=none Cq-Depend: chromium:2607150 Change-Id: I761ecdd8811e5612b39e96c73442cc796361d0f0 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_commands.h 2 files changed, 359 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/49113/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index ed7f97d..dbe9b75 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -3,6 +3,7 @@ #include <stdint.h> #include <string.h> #include <assert.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <delay.h> #include <device/device.h> @@ -994,8 +995,22 @@ bool google_chromeec_get_ap_watchdog_flag(void) { struct ec_response_uptime_info resp; - return (!google_chromeec_get_uptime_info(&resp) && - (resp.ec_reset_flags & EC_RESET_FLAG_AP_WATCHDOG)); + int last_idx; + + if (google_chromeec_get_uptime_info(&resp)) + return false; + + if (resp.ec_reset_flags & EC_RESET_FLAG_AP_WATCHDOG) + return true; + + last_idx = MIN(resp.ap_resets_since_ec_boot, + ARRAY_SIZE(resp.recent_ap_reset)) - 1; + if (last_idx >= 0 && + resp.recent_ap_reset[last_idx].reset_cause == + CHIPSET_RESET_AP_WATCHDOG) + return true; + + return false; } int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index fb83d60..39e1cec 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -29,7 +29,10 @@ #include "compile_time_macros.h" #else +/* If BUILD_ASSERT isn't already defined, make it a no-op */ +#ifndef BUILD_ASSERT #define BUILD_ASSERT(_cond) +#endif /* !BUILD_ASSERT */ #endif /* CHROMIUM_EC */ #ifdef __KERNEL__ @@ -50,6 +53,21 @@ #define BIT_ULL(nr) (1ULL << (nr)) #endif +/* + * When building Zephyr, this file ends up being included before Zephyr's + * include/sys/util.h so causes a warning there. We don't want to add an #ifdef + * in that file since it won't be accepted upstream. So work around it here. + */ +#ifndef CONFIG_ZEPHYR +#ifndef GENMASK +#define GENMASK(h, l) (((BIT(h) << 1) - 1) ^ (BIT(l) - 1)) +#endif + +#ifndef GENMASK_ULL +#define GENMASK_ULL(h, l) (((BIT_ULL(h) << 1) - 1) ^ (BIT_ULL(l) - 1)) +#endif +#endif + #endif /* __KERNEL__ */ /* @@ -1388,7 +1406,7 @@ */ EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, /* - * Early Firmware Selection ver.2. Enabled by VBOOT_EFS2 config option. + * Early Firmware Selection ver.2. Enabled by CONFIG_VBOOT_EFS2. * Note this is a RO feature. So, a query (EC_CMD_GET_FEATURES) should * be sent to RO to be precise. */ @@ -1397,6 +1415,18 @@ EC_FEATURE_SCP = 39, /* The MCU is an Integrated Sensor Hub */ EC_FEATURE_ISH = 40, + /* New TCPMv2 TYPEC_ prefaced commands supported */ + EC_FEATURE_TYPEC_CMD = 41, + /* + * The EC will wait for direction from the AP to enter Type-C alternate + * modes or USB4. + */ + EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY = 42, + /* + * The EC will wait for an acknowledge from the AP after setting the + * mux. + */ + EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43, }; #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) @@ -2599,6 +2629,11 @@ MOTIONSENSE_ORIENTATION_UNKNOWN = 4, }; +struct ec_response_activity_data { + uint8_t activity; /* motionsensor_activity */ + uint8_t state; +} __ec_todo_packed; + struct ec_response_motion_sensor_data { /* Flags for each sensor. */ uint8_t flags; @@ -2606,17 +2641,16 @@ uint8_t sensor_num; /* Each sensor is up to 3-axis. */ union { - int16_t data[3]; + int16_t data[3]; /* for sensors using unsigned data */ - uint16_t udata[3]; + uint16_t udata[3]; struct __ec_todo_packed { - uint16_t reserved; - uint32_t timestamp; + uint16_t reserved; + uint32_t timestamp; }; struct __ec_todo_unpacked { - uint8_t activity; /* motionsensor_activity */ - uint8_t state; - int16_t add_info[2]; + struct ec_response_activity_data activity_data; + int16_t add_info[2]; }; }; } __ec_todo_packed; @@ -2864,8 +2898,19 @@ /* Ignored, used for alignment. */ uint8_t reserved; - /* Individual component values to spoof. */ - int16_t components[3]; + union { + /* Individual component values to spoof. */ + int16_t components[3]; + + /* Used when spoofing an activity */ + struct { + /* enum motionsensor_activity */ + uint8_t activity_num; + + /* spoof activity state */ + uint8_t activity_state; + }; + }; } spoof; /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ @@ -3768,6 +3813,7 @@ #define EC_MKBP_LID_OPEN 0 #define EC_MKBP_TABLET_MODE 1 #define EC_MKBP_BASE_ATTACHED 2 +#define EC_MKBP_FRONT_PROXIMITY 3 /* Run keyboard factory test scanning */ #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 @@ -4637,6 +4683,7 @@ EC_DEVICE_EVENT_TRACKPAD, EC_DEVICE_EVENT_DSP, EC_DEVICE_EVENT_WIFI, + EC_DEVICE_EVENT_WLC, }; enum ec_device_event_param { @@ -5183,6 +5230,7 @@ EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_IDLE flag */ + EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */ }; /* Flags for ec_params_reboot_ec.reboot_flags */ @@ -5395,10 +5443,6 @@ /* Active Link Uni-Direction */ #define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) -/* - * Underdevelopement : - * Please remove this tag if using _v2 outside platform/ec - */ struct ec_response_usb_pd_control_v2 { uint8_t enabled; uint8_t role; @@ -5408,8 +5452,7 @@ uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ uint8_t reserved; /* Reserved for future use */ uint8_t control_flags; /* USB_PD_CTRL_*flags */ - /* TODO: b:158234949 Add definitions for cable speed */ - uint8_t cable_speed; /* USB_R30_SS/TBT_SS_* cable speed */ + uint8_t cable_speed; /* TBT_SS_* cable speed */ uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ } __ec_align1; @@ -5833,7 +5876,7 @@ */ #define EC_CMD_GET_UPTIME_INFO 0x0121 -/* Reset causes */ +/* EC reset causes */ #define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */ #define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */ #define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */ @@ -5862,6 +5905,72 @@ #define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ #define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ +/* + * Reason codes used by the AP after a shutdown to figure out why it was reset + * by the EC. These are sent in EC commands. Therefore, to maintain protocol + * compatibility: + * - New entries must be inserted prior to the _COUNT field + * - If an existing entry is no longer in service, it must be replaced with a + * RESERVED entry instead. + * - The semantic meaning of an entry should not change. + * - Do not exceed 2^15 - 1 for reset reasons or 2^16 - 1 for shutdown reasons. + */ +enum chipset_reset_reason { + CHIPSET_RESET_BEGIN = 0, + CHIPSET_RESET_UNKNOWN = CHIPSET_RESET_BEGIN, + /* Custom reason defined by a board.c or baseboard.c file */ + CHIPSET_RESET_BOARD_CUSTOM, + /* Believe that the AP has hung */ + CHIPSET_RESET_HANG_REBOOT, + /* Reset by EC console command */ + CHIPSET_RESET_CONSOLE_CMD, + /* Reset by EC host command */ + CHIPSET_RESET_HOST_CMD, + /* Keyboard module reset key combination */ + CHIPSET_RESET_KB_SYSRESET, + /* Keyboard module warm reboot */ + CHIPSET_RESET_KB_WARM_REBOOT, + /* Debug module warm reboot */ + CHIPSET_RESET_DBG_WARM_REBOOT, + /* I cannot self-terminate. You must lower me into the steel. */ + CHIPSET_RESET_AP_REQ, + /* Reset as side-effect of startup sequence */ + CHIPSET_RESET_INIT, + /* EC detected an AP watchdog event. */ + CHIPSET_RESET_AP_WATCHDOG, + + CHIPSET_RESET_COUNT, +}; + +/* + * AP hard shutdowns are logged on the same path as resets. + */ +enum chipset_shutdown_reason { + CHIPSET_SHUTDOWN_BEGIN = BIT(15), + CHIPSET_SHUTDOWN_POWERFAIL = CHIPSET_SHUTDOWN_BEGIN, + /* Forcing a shutdown as part of EC initialization */ + CHIPSET_SHUTDOWN_INIT, + /* Custom reason on a per-board basis. */ + CHIPSET_SHUTDOWN_BOARD_CUSTOM, + /* This is a reason to inhibit startup, not cause shut down. */ + CHIPSET_SHUTDOWN_BATTERY_INHIBIT, + /* A power_wait_signal is being asserted */ + CHIPSET_SHUTDOWN_WAIT, + /* Critical battery level. */ + CHIPSET_SHUTDOWN_BATTERY_CRIT, + /* Because you told me to. */ + CHIPSET_SHUTDOWN_CONSOLE_CMD, + /* Forcing a shutdown to effect entry to G3. */ + CHIPSET_SHUTDOWN_G3, + /* Force shutdown due to over-temperature. */ + CHIPSET_SHUTDOWN_THERMAL, + /* Force a chipset shutdown from the power button through EC */ + CHIPSET_SHUTDOWN_BUTTON, + + CHIPSET_SHUTDOWN_COUNT, +}; + + struct ec_response_uptime_info { /* * Number of milliseconds since the last EC boot. Sysjump resets @@ -5889,10 +5998,7 @@ /* Empty log entries have both the cause and timestamp set to zero. */ struct ap_reset_log_entry { - /* - * See include/chipset.h: enum chipset_{reset,shutdown}_reason - * for details. - */ + /* See enum chipset_{reset,shutdown}_reason for details. */ uint16_t reset_cause; /* Reserved for protocol growth. */ @@ -6012,13 +6118,21 @@ * * This command is used for validation purpose, where the AP needs to be * returned back to S0 state from G3 state without using the servo to trigger - * wake events.For this,there is no request or response struct. - * - * Order of command usage: - * ectool reboot_ap_on_g3 && shutdown -h now + * wake events. + * - With command version 0: + * AP reboots immediately from G3 + * command usage: ectool reboot_ap_on_g3 && shutdown -h now + * - With command version 1: + * AP reboots after the user specified delay + * command usage: ectool reboot_ap_on_g3 [<delay>] && shutdown -h now */ #define EC_CMD_REBOOT_AP_ON_G3 0x0127 +struct ec_params_reboot_ap_on_g3_v1 { + /* configurable delay in seconds in G3 state */ + uint32_t reboot_ap_at_g3_delay; +} __ec_align4; + /*****************************************************************************/ /* Get PD port capabilities * @@ -6366,6 +6480,14 @@ enum typec_control_command { TYPEC_CONTROL_COMMAND_EXIT_MODES, TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, + TYPEC_CONTROL_COMMAND_ENTER_MODE, +}; + +/* Modes (USB or alternate) that a type-C port may enter. */ +enum typec_mode { + TYPEC_MODE_DP, + TYPEC_MODE_TBT, + TYPEC_MODE_USB4, }; struct ec_params_typec_control { @@ -6380,6 +6502,7 @@ */ union { uint32_t clear_events_mask; + uint8_t mode_to_enter; /* enum typec_mode */ uint8_t placeholder[128]; }; } __ec_align1; @@ -6393,9 +6516,6 @@ * EC_CMD_USB_PD_CONTROL command. * * This also combines in the EC_CMD_USB_PD_MUX_INFO flags. - * - * Version 0 of command is under development - * TODO(b/167700356): Remove this statement when version 0 is finalized */ #define EC_CMD_TYPEC_STATUS 0x0133 @@ -6469,33 +6589,183 @@ #define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) #define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) +/* + * Encode and decode for BCD revision response + * + * Note: the major revision set is written assuming that the value given is the + * Specification Revision from the PD header, which currently only maps to PD + * 1.0-3.0 with the major revision being one greater than the binary value. + */ +#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12) +#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF) +#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF) + +/* + * Decode helpers for Source and Sink Capability PDOs + * + * Note: The Power Delivery Specification should be considered the ultimate + * source of truth on the decoding of these PDOs + */ +#define PDO_TYPE_FIXED (0 << 30) +#define PDO_TYPE_BATTERY (1 << 30) +#define PDO_TYPE_VARIABLE (2 << 30) +#define PDO_TYPE_AUGMENTED (3 << 30) +#define PDO_TYPE_MASK (3 << 30) + +/* + * From Table 6-9 and Table 6-14 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Fixed Supply + * <29> : Dual-Role Power + * <28> : SNK/SRC dependent + * <27> : Unconstrained Power + * <26> : USB Communications Capable + * <25> : Dual-Role Data + * <24:20> : SNK/SRC dependent + * <19:10> : Voltage in 50mV Units + * <9:0> : Maximum Current in 10mA units + */ +#define PDO_FIXED_DUAL_ROLE BIT(29) +#define PDO_FIXED_UNCONSTRAINED BIT(27) +#define PDO_FIXED_COMM_CAP BIT(26) +#define PDO_FIXED_DATA_SWAP BIT(25) +#define PDO_FIXED_FRS_CURR_MASK GENMASK(24, 23) /* Sink Cap only */ +#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10) + +/* + * From Table 6-12 and Table 6-16 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Battery + * <29:20> : Maximum Voltage in 50mV units + * <19:10> : Minimum Voltage in 50mV units + * <9:0> : Maximum Allowable Power in 250mW units + */ +#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250) + +/* + * From Table 6-11 and Table 6-15 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Variable Supply (non-Battery) + * <29:20> : Maximum Voltage in 50mV units + * <19:10> : Minimum Voltage in 50mV units + * <9:0> : Operational Current in 10mA units + */ +#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10) + +/* + * From Table 6-13 and Table 6-17 PD Rev 3.0 Ver 2.0 + * + * Note this type is reserved in PD 2.0, and only one type of APDO is + * supported as of the cited version. + * + * <31:30> : Augmented Power Data Object + * <29:28> : Programmable Power Supply + * <27> : PPS Power Limited + * <26:25> : Reserved + * <24:17> : Maximum Voltage in 100mV increments + * <16> : Reserved + * <15:8> : Minimum Voltage in 100mV increments + * <7> : Reserved + * <6:0> : Maximum Current in 50mA increments + */ +#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100) +#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100) +#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50) + struct ec_params_typec_status { uint8_t port; } __ec_align1; struct ec_response_typec_status { - uint8_t pd_enabled; /* PD communication enabled - bool */ - uint8_t dev_connected; /* Device connected - bool */ - uint8_t sop_connected; /* Device is SOP PD capable - bool */ - uint8_t reserved1; /* Reserved for future use */ + uint8_t pd_enabled; /* PD communication enabled - bool */ + uint8_t dev_connected; /* Device connected - bool */ + uint8_t sop_connected; /* Device is SOP PD capable - bool */ + uint8_t source_cap_count; /* Number of Source Cap PDOs */ - uint8_t power_role; /* enum pd_power_role */ - uint8_t data_role; /* enum pd_data_role */ - uint8_t vconn_role; /* enum pd_vconn_role */ - uint8_t reserved2; /* Reserved for future use */ + uint8_t power_role; /* enum pd_power_role */ + uint8_t data_role; /* enum pd_data_role */ + uint8_t vconn_role; /* enum pd_vconn_role */ + uint8_t sink_cap_count; /* Number of Sink Cap PDOs */ - uint8_t polarity; /* enum tcpc_cc_polarity */ - uint8_t cc_state; /* enum pd_cc_states */ - uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ - uint8_t mux_state; /* USB_PD_MUX* - encoded USB mux state */ + uint8_t polarity; /* enum tcpc_cc_polarity */ + uint8_t cc_state; /* enum pd_cc_states */ + uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ + uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */ - char tc_state[32]; /* TC state name */ + char tc_state[32]; /* TC state name */ - uint32_t events; /* PD_STATUS_EVENT bitmask */ + uint32_t events; /* PD_STATUS_EVENT bitmask */ - /* TODO(b/167700356): Add revisions and source cap PDOs */ + /* + * BCD PD revisions for partners + * + * The format has the PD major reversion in the upper nibble, and PD + * minor version in the next nibble. Following two nibbles are + * currently 0. + * ex. PD 3.2 would map to 0x3200 + * + * PD major/minor will be 0 if no PD device is connected. + */ + uint16_t sop_revision; + uint16_t sop_prime_revision; + + uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */ + + uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */ } __ec_align1; +/** + * Get the number of peripheral charge ports + */ +#define EC_CMD_PCHG_COUNT 0x0134 + +#define EC_PCHG_MAX_PORTS 8 + +struct ec_response_pchg_count { + uint8_t port_count; +} __ec_align1; + +/** + * Get the status of a peripheral charge port + */ +#define EC_CMD_PCHG 0x0135 + +struct ec_params_pchg { + uint8_t port; +} __ec_align1; + +struct ec_response_pchg { + uint32_t error; /* enum pchg_error */ + uint8_t state; /* enum pchg_state state */ + uint8_t battery_percentage; +} __ec_align2; + +enum pchg_state { + /* Charger is reset and not initialized. */ + PCHG_STATE_RESET = 0, + /* Charger is initialized or disabled. */ + PCHG_STATE_INITIALIZED, + /* Charger is enabled and ready to detect a device. */ + PCHG_STATE_ENABLED, + /* Device is detected in proximity. */ + PCHG_STATE_DETECTED, + /* Device is being charged. */ + PCHG_STATE_CHARGING, +}; + +#define EC_PCHG_STATE_TEXT { \ + [PCHG_STATE_RESET] = "RESET", \ + [PCHG_STATE_INITIALIZED] = "INITIALIZED", \ + [PCHG_STATE_ENABLED] = "ENABLED", \ + [PCHG_STATE_DETECTED] = "DETECTED", \ + [PCHG_STATE_CHARGING] = "CHARGING", \ + } + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ @@ -6841,6 +7111,28 @@ uint32_t cycle_count; } __ec_align4; +/** + * struct ec_response_battery_static_info_v1 - hostcmd v1 battery static info + * Equivalent to struct ec_response_battery_static_info, but with longer + * strings. + * @design_capacity: battery design capacity (in mAh) + * @design_voltage: battery design voltage (in mV) + * @cycle_count: battery cycle count + * @manufacturer_ext: battery manufacturer string + * @model_ext: battery model string + * @serial_ext: battery serial number string + * @type_ext: battery type string + */ +struct ec_response_battery_static_info_v1 { + uint16_t design_capacity; + uint16_t design_voltage; + uint32_t cycle_count; + char manufacturer_ext[12]; + char model_ext[12]; + char serial_ext[12]; + char type_ext[12]; +} __ec_align4; + /* * Get battery dynamic information, i.e. information that is likely to change * every time it is read. @@ -6896,6 +7188,13 @@ uint8_t allow_charging; } __ec_align_size1; +/* Get ACK from the USB-C SS muxes */ +#define EC_CMD_USB_PD_MUX_ACK 0x0603 + +struct ec_params_usb_pd_mux_ack { + uint8_t port; /* USB-C port number */ +} __ec_align1; + /*****************************************************************************/ /* * Reserve a range of host commands for board-specific, experimental, or -- To view, visit https://review.coreboot.org/c/coreboot/+/49113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I761ecdd8811e5612b39e96c73442cc796361d0f0 Gerrit-Change-Number: 49113 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2021