coreboot-gerrit January 2021

coreboot-gerrit@coreboot.org

1 participants
6507 discussions

Change in coreboot[master]: mb/google/dedede/var/sasuke: Enable audio feature
by shkim (Code Review) 08 Jan '21

08 Jan '21

Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/49160 to review the following change. Change subject: mb/google/dedede/var/sasuke: Enable audio feature ...................................................................... mb/google/dedede/var/sasuke: Enable audio feature This change adds DA7219 audio codec and MAX98360A amplifier for sasuke. BUG=None Change-Id: Ib48eb74fbfe171d46d0d23859057ba169b56bde2 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/sasuke/overridetree.cb 1 file changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/49160/1 diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb index 69ea1e1..ca5de56 100644 --- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -52,7 +52,31 @@ device pci 15.0 on end device pci 15.2 on end device pci 1c.7 on end - device pci 19.0 on end - device pci 1f.3 on end + device pci 19.0 on + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/49160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib48eb74fbfe171d46d0d23859057ba169b56bde2 Gerrit-Change-Number: 49160 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/dedede/var/sasuke: Configure GPIO NC pads
by shkim (Code Review) 08 Jan '21

08 Jan '21

Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/49139 to review the following change. Change subject: mb/google/dedede/var/sasuke: Configure GPIO NC pads ...................................................................... mb/google/dedede/var/sasuke: Configure GPIO NC pads Configure GPIO NC pads for sasuke. BUG=b:172104731 Change-Id: I3bf8f97708536010da82402ea3d49e387e732d61 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- A src/mainboard/google/dedede/variants/sasuke/Makefile.inc A src/mainboard/google/dedede/variants/sasuke/gpio.c 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/49139/1 diff --git a/src/mainboard/google/dedede/variants/sasuke/Makefile.inc b/src/mainboard/google/dedede/variants/sasuke/Makefile.inc new file mode 100644 index 0000000..eb2c9bc --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/sasuke/gpio.c b/src/mainboard/google/dedede/variants/sasuke/gpio.c new file mode 100644 index 0000000..cdce776 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/gpio.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* A11 : TOUCH_RPT_EN ==> NC */ + PAD_NC(GPP_A11, NONE), + + /* B8 : WLAN_CLKREQ_ODL ==> NC */ + PAD_NC(GPP_B8, NONE), + + /* C18 : AP_I2C_EMR_SDA ==> NC */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL ==> NC */ + PAD_NC(GPP_C19, NONE), + + /* D1 : WLAN_PERST_L ==> NC */ + PAD_NC(GPP_D1, NONE), + /* D3 : WLAN_PCIE_WAKE_ODL ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D4 : TOUCH_INT_ODL ==> NC */ + PAD_NC(GPP_D4, NONE), + /* D5 : TOUCH_RESET_L ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D6 : EN_PP3300_TOUCH_S0 ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D12 : WCAM_RST_L ==> NC */ + PAD_NC(GPP_D12, NONE), + /* D14 : EN_PP1200_CAMERA ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 ==> NC */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 ==> NC */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 ==> NC */ + PAD_NC(GPP_D21, NONE), + + /* E2 : CLK_24M_WCAM ==> NC */ + PAD_NC(GPP_E2, NONE), + + /* G7 : SD_SDIO_WP ==> NC */ + PAD_NC(GPP_G7, NONE), + + /* H4 : AP_I2C_TS_SDA ==> NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : AP_I2C_TS_SCL ==> NC */ + PAD_NC(GPP_H5, NONE), + /* H6 : AP_I2C_CAM_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + + /* S2 : DMIC1_CLK ==> NC */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA ==> NC */ + PAD_NC(GPP_S3, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/49139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bf8f97708536010da82402ea3d49e387e732d61 Gerrit-Change-Number: 49139 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/asrock/h110m: Drop DEVICETREE from Kconfig
by Felix Singer (Code Review) 08 Jan '21

08 Jan '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49183 ) Change subject: mb/asrock/h110m: Drop DEVICETREE from Kconfig ...................................................................... mb/asrock/h110m: Drop DEVICETREE from Kconfig Drop DEVICETREE from Kconfig since its value is the default. Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Change-Id: Idbcd49cca6494ae2da0f364c24638d7ca11911da Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/asrock/h110m/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/49183/1 diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index d923c30..c4b48c3 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -33,10 +33,6 @@ int default 8 -config DEVICETREE - string - default "devicetree.cb" - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xd00 -- To view, visit https://review.coreboot.org/c/coreboot/+/49183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbcd49cca6494ae2da0f364c24638d7ca11911da Gerrit-Change-Number: 49183 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/clevo/cml-u: Drop VGA_BIOS_FILE from Kconfig
by Felix Singer (Code Review) 08 Jan '21

08 Jan '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49138 ) Change subject: mb/clevo/cml-u: Drop VGA_BIOS_FILE from Kconfig ...................................................................... mb/clevo/cml-u: Drop VGA_BIOS_FILE from Kconfig It doesn't make sense to configure that filename in Kconfig, since the filename can be changed either and is chosen by the user. So remove it. Change-Id: I3eed05637da29096bc1d134505d7335db5db1439 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/49138/1 diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index f8bf1ba..5653fb4 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -66,10 +66,6 @@ int default 512 -config VGA_BIOS_FILE - string - default "pci8086,9b41.rom" - config VGA_BIOS_ID string default "8086,9b41" -- To view, visit https://review.coreboot.org/c/coreboot/+/49138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3eed05637da29096bc1d134505d7335db5db1439 Gerrit-Change-Number: 49138 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: ec/google/chromeec: add SSFC CBI support
by Marco Chen (Code Review) 08 Jan '21

08 Jan '21

Marco Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48791 ) Change subject: ec/google/chromeec: add SSFC CBI support ...................................................................... ec/google/chromeec: add SSFC CBI support An API is added to get SSFC value from cros EC. BUG=b:174118027 BRANCH=octopus TEST=check SSFC value from EC is correct compared to value in CBI Change-Id: Ifd521514bbc2e90c789f3760b72e8326e614e2b1 --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/48791/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index ed7f97d..fdbe582 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -863,6 +863,11 @@ return cbi_get_uint32(version, CBI_TAG_BOARD_VERSION); } +int google_chromeec_cbi_get_ssfc(uint32_t *ssfc) +{ + return cbi_get_uint32(ssfc, CBI_TAG_SSFC); +} + static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag) { struct ec_params_get_cbi params = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index c3c456f..7c41f04 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -89,6 +89,7 @@ /* version may be stored in CBI as a smaller integer width, but the EC code handles it correctly. */ int google_chromeec_cbi_get_board_version(uint32_t *version); +int google_chromeec_cbi_get_ssfc(uint32_t *ssfc); #define CROS_SKU_UNKNOWN 0xFFFFFFFF #define CROS_SKU_UNPROVISIONED 0x7FFFFFFF -- To view, visit https://review.coreboot.org/c/coreboot/+/48791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd521514bbc2e90c789f3760b72e8326e614e2b1 Gerrit-Change-Number: 48791 Gerrit-PatchSet: 1 Gerrit-Owner: Marco Chen <marcochen(a)google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/common/uart: Restrict scope of uart_common_init to uart.c
by Furquan Shaikh (Code Review) 08 Jan '21

08 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49211 ) Change subject: soc/intel/common/uart: Restrict scope of uart_common_init to uart.c ...................................................................... soc/intel/common/uart: Restrict scope of uart_common_init to uart.c uart_common_init is not used outside of soc/intel/common/block/uart.c. This change restricts the scope to this file and drops the declaration from uart.h Change-Id: I499a53506f9b2e91ecc7334bf9b023d342e802fc Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/uart.c 2 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/49211/1 diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index 87fdf68..fd65f4c 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -24,12 +24,6 @@ */ /* - * Common routine to initialize UART controller PCI config space, take it out of - * reset and configure M/N dividers. - */ -void uart_common_init(const struct device *dev, uintptr_t baseaddr); - -/* * Check if UART debug controller is initialized * Returns: * true = If debug controller PCI config space is initialized and device is diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 75c16d4..1e205ef 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -58,7 +58,7 @@ return UART_CONSOLE_INVALID_INDEX; } -void uart_common_init(const struct device *device, uintptr_t baseaddr) +static void uart_common_init(const struct device *device, uintptr_t baseaddr) { #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCI_BDF(device); -- To view, visit https://review.coreboot.org/c/coreboot/+/49211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I499a53506f9b2e91ecc7334bf9b023d342e802fc Gerrit-Change-Number: 49211 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: soc/intel/common: Pass in pci_devfn_t into lpss_set_power
by Furquan Shaikh (Code Review) 08 Jan '21

08 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49210 ) Change subject: soc/intel/common: Pass in pci_devfn_t into lpss_set_power ...................................................................... soc/intel/common: Pass in pci_devfn_t into lpss_set_power This change updates the parameter passed into `lpss_set_power()` from struct device * to pci_devfn_t. This allows the users in the early stages to use pci_devfn_t instead of having to walk the device tree to get a pointer to the relevant device structure. It is important for optimizing out unnecessary components of the device tree from the early stages. Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/lpss.h M src/soc/intel/common/block/lpss/lpss.c M src/soc/intel/common/block/uart/uart.c 5 files changed, 10 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/49210/1 diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 8363713..395a14d 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -448,7 +448,6 @@ int devfn; uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol; struct gspi_ctrlr_params params, *p = &params; - const struct device *device; /* Only chip select 0 is supported. */ if (dev->cs != 0) { @@ -468,14 +467,9 @@ } devfn = gspi_soc_bus_to_devfn(p->gspi_bus); - /* - * devfn is already validated as part of gspi_ctrlr_params_init. - * No need to revalidate it again. - */ - device = pcidev_path_on_root(devfn); /* Ensure controller is in D0 state */ - lpss_set_power_state(device, STATE_D0); + lpss_set_power_state(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)), STATE_D0); /* Take controller out of reset, keeping DMA in reset. */ gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET); diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 5aa7729..57e5d5e 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -38,7 +38,6 @@ static int lpss_i2c_early_init_bus(unsigned int bus) { const struct dw_i2c_bus_config *config; - const struct device *tree_dev; pci_devfn_t dev; int devfn; uintptr_t base; @@ -52,11 +51,6 @@ /* Look up the controller device in the devicetree */ dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - tree_dev = pcidev_path_on_root(devfn); - if (!tree_dev || !tree_dev->enabled) { - printk(BIOS_ERR, "I2C%u device not enabled\n", bus); - return -1; - } /* Skip if not enabled for early init */ config = dw_i2c_get_soc_cfg(bus); @@ -75,7 +69,7 @@ lpss_reset_release(base); /* Ensure controller is in D0 state */ - lpss_set_power_state(tree_dev, STATE_D0); + lpss_set_power_state(dev, STATE_D0); /* Initialize the controller */ if (dw_i2c_init(bus, config) < 0) { @@ -153,7 +147,7 @@ return; /* Ensure controller is in D0 state */ - lpss_set_power_state(dev, STATE_D0); + lpss_set_power_state(PCI_BDF(dev), STATE_D0); /* Take device out of reset if its not done before */ if (lpss_is_controller_in_reset(base_address)) diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index 145857c..8d22e7a 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -25,7 +25,7 @@ bool lpss_is_controller_in_reset(uintptr_t base); /* Set controller power state to D0 or D3*/ -void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state); +void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state); /* * Handler to get list of LPSS controllers. The SOC is expected to send out a diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 74c7aa1..6e33c0f 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -65,16 +65,12 @@ } /* Set controller power state to D0 or D3 */ -void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state) +void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state) { -#if defined(__SIMPLE_DEVICE__) - unsigned int devfn = dev->path.pci.devfn; - pci_devfn_t lpss_dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); -#else - const struct device *lpss_dev = dev; -#endif - - pci_update_config8(lpss_dev, PME_CTRL_STATUS, ~POWER_STATE_MASK, state); + uint8_t reg8 = pci_s_read_config8(devfn, PME_CTRL_STATUS); + reg8 &= ~POWER_STATE_MASK; + reg8 |= state; + pci_s_write_config8(devfn, PME_CTRL_STATUS, reg8); } bool is_dev_lpss(const struct device *dev) diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 142a936..75c16d4 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -26,7 +26,7 @@ static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr) { /* Ensure controller is in D0 state */ - lpss_set_power_state(dev, STATE_D0); + lpss_set_power_state(PCI_BDF(dev), STATE_D0); /* Take UART out of reset */ lpss_reset_release(baseaddr); -- To view, visit https://review.coreboot.org/c/coreboot/+/49210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f Gerrit-Change-Number: 49210 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range()
by Furquan Shaikh (Code Review) 08 Jan '21

08 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49209 ) Change subject: soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range() ...................................................................... soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range() This change drops the parameter `struct device *dev` from the function `soc_get_gen_io_dec_range()`. This function uses the parameter dev to get a pointer to config structure for extracting the decode ranges configured by mainboard in device tree. However, there is no separate chip driver for the LPC device which means that the SoC code can use `config_of_soc()` to get to SoC chip config instead of using the LPC device. This change is being done in preparation to clean up the device tree/chip config access in early stages that allows for optimizing the inclusion of device tree elements in the early stages. Change-Id: I3ea53ddc771f592dd0ea5e5e809be2d2eff7f16d Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/alderlake/espi.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/lpc.c 10 files changed, 18 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/49209/1 diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index c909030..b237727 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -35,9 +35,9 @@ return lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index b21c117..c8e35c4 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -33,9 +33,9 @@ return cnl_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 2fdcdef..82cba8e 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -98,8 +98,7 @@ /* Enable PCH LPC by setting up generic decode range registers. */ void pch_enable_lpc(void); /* Get SoC's generic IO decoder range register settings. */ -void soc_get_gen_io_dec_range(const struct device *dev, - uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); /* Mirror generic IO decoder range register settings into DMI PCR. */ void soc_setup_dmi_pcr_io_dec(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); /* Add resource into LPC PCI device space */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 67dd661..d050ee3 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -270,15 +270,9 @@ void pch_enable_lpc(void) { - /* Lookup device tree in romstage */ - const struct device *dev; uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]; - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); - if (!dev) - return; - - soc_get_gen_io_dec_range(dev, gen_io_dec); + soc_get_gen_io_dec_range(gen_io_dec); lpc_set_gen_decode_range(gen_io_dec); soc_setup_dmi_pcr_io_dec(gen_io_dec); if (ENV_PAYLOAD_LOADER) diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index a531fcc..8f82755 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -31,9 +31,9 @@ return ehl_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 7f9ff2f..4107d7e 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -32,9 +32,9 @@ return icl_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index 0977857..11299a9 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -32,9 +32,9 @@ return jsl_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index f9c6639..b83fadd 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -29,9 +29,9 @@ return skl_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index acd3b12..8602b0d 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -38,9 +38,9 @@ return tgl_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 3169545..dee99b7 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -18,9 +18,9 @@ return xeon_lpc_fixed_mmio_ranges; } -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; -- To view, visit https://review.coreboot.org/c/coreboot/+/49209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ea53ddc771f592dd0ea5e5e809be2d2eff7f16d Gerrit-Change-Number: 49209 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: cpu/x86/smm: Use append instead of assign for smm-c-deps
by Furquan Shaikh (Code Review) 08 Jan '21

08 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49208 ) Change subject: cpu/x86/smm: Use append instead of assign for smm-c-deps ...................................................................... cpu/x86/smm: Use append instead of assign for smm-c-deps This change uses append operation (+=) instead of assignment (:=) for smm-c-deps to ensure that any earlier assignment is not overwritten. Change-Id: Ic1d62b414cfe3f61ee2b80b026b7338faa186904 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/cpu/x86/smm/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/49208/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index eb386a6..1ed018d 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -17,7 +17,7 @@ smmstub-generic-ccopts += -D__SMM__ smm-generic-ccopts += -D__SMM__ -smm-c-deps:=$$(OPTION_TABLE_H) +smm-c-deps+=$$(OPTION_TABLE_H) $(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(filter-out %.ld, $(smm-objs)) --no-whole-archive $(COMPILER_RT_smm) --end-group -- To view, visit https://review.coreboot.org/c/coreboot/+/49208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1d62b414cfe3f61ee2b80b026b7338faa186904 Gerrit-Change-Number: 49208 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

6 6

Change in coreboot[master]: soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports
by John Zhao (Code Review) 08 Jan '21

08 Jan '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49052 ) Change subject: soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports ...................................................................... soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI USB2 port reset event issued by the xHCI driver shall trigger a message upstream to CPU to wake it from the low power state which allows a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Built and booted to kernel on Voxel board. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f --- M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/usb.h 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/49052/1 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index ed34897..295f789 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -159,6 +159,9 @@ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; else params->Usb2OverCurrentPin[i] = 0xff; + + if (config->usb2_ports[i].type_c) + params->PortResetMessageEnable[i] = 1; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { diff --git a/src/soc/intel/tigerlake/include/soc/usb.h b/src/soc/intel/tigerlake/include/soc/usb.h index 69b5ca8..5dea4bf 100644 --- a/src/soc/intel/tigerlake/include/soc/usb.h +++ b/src/soc/intel/tigerlake/include/soc/usb.h @@ -31,6 +31,7 @@ uint8_t tx_emp_enable; uint8_t pre_emp_bias; uint8_t pre_emp_bit; + uint8_t type_c; }; /* USB Overcurrent pins definition */ @@ -112,6 +113,7 @@ .tx_emp_enable = USB2_PRE_EMP_ON, \ .pre_emp_bias = USB2_BIAS_56P3MV, \ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + .type_c = 1, \ } struct usb3_port_config { -- To view, visit https://review.coreboot.org/c/coreboot/+/49052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f Gerrit-Change-Number: 49052 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

4 3

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2021