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Change in coreboot[master]: payloads/external: Update cbfs-ints with CONFIG_UPDATE_IMAGE
by Arthur Heymans (Code Review) 08 Jan '21

08 Jan '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48898 ) Change subject: payloads/external: Update cbfs-ints with CONFIG_UPDATE_IMAGE ...................................................................... payloads/external: Update cbfs-ints with CONFIG_UPDATE_IMAGE Change-Id: Icfbfff3ba680a85eb2f683867064b19f40b9d40f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/Makefile.inc 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/48898/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 119b4dd..b9a6314 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -101,21 +101,21 @@ ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) -ifneq ($(CONFIG_UPDATE_IMAGE),y) PHONY+=seabios_ps2_timeout INTERMEDIATE+=seabios_ps2_timeout seabios_ps2_timeout: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" + $(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/ps2-keyboard-spinup 2>/dev/null) $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup endif endif -endif ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) PHONY+=seabios_sercon INTERMEDIATE+=seabios_sercon seabios_sercon: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Add sercon-port file\n" + $(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/sercon-port 2>/dev/null) $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port endif @@ -124,6 +124,7 @@ INTERMEDIATE+=seabios_thread_optionroms seabios_thread_optionroms: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Thread optionroms\n" + $(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/threads 2>/dev/null) $(CBFSTOOL) $< add-int -i 2 -n etc/threads endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfbfff3ba680a85eb2f683867064b19f40b9d40f Gerrit-Change-Number: 48898 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: */Makefile.inc: Add some INTERMEDIATE targets to .PHONY
by Arthur Heymans (Code Review) 08 Jan '21

08 Jan '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48897 ) Change subject: */Makefile.inc: Add some INTERMEDIATE targets to .PHONY ...................................................................... */Makefile.inc: Add some INTERMEDIATE targets to .PHONY Change-Id: I125e40204f3a9602ee5810d341ef40f9f50d045b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/Makefile.inc M src/cpu/intel/fit/Makefile.inc M src/security/intel/cbnt/Makefile.inc M src/security/intel/txt/Makefile.inc M src/soc/intel/common/block/fast_spi/Makefile.inc M src/southbridge/intel/common/firmware/Makefile.inc 6 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/48897/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 823cd87..119b4dd 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -102,6 +102,7 @@ ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) ifneq ($(CONFIG_UPDATE_IMAGE),y) +PHONY+=seabios_ps2_timeout INTERMEDIATE+=seabios_ps2_timeout seabios_ps2_timeout: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" @@ -111,6 +112,7 @@ endif ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) +PHONY+=seabios_sercon INTERMEDIATE+=seabios_sercon seabios_sercon: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Add sercon-port file\n" @@ -118,6 +120,7 @@ endif ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) +PHONY+=seabios_thread_optionroms INTERMEDIATE+=seabios_thread_optionroms seabios_thread_optionroms: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Thread optionroms\n" diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc index 9866684..20483d8 100644 --- a/src/cpu/intel/fit/Makefile.inc +++ b/src/cpu/intel/fit/Makefile.inc @@ -6,6 +6,7 @@ ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y) +PHONY+=add_mcu_fit INTERMEDIATE+=add_mcu_fit add_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) @printf " UPDATE-FIT Microcode\n" @@ -14,6 +15,7 @@ # Second FIT in TOP_SWAP bootblock ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) +PHONY+=add_ts_mcu_fit INTERMEDIATE+=add_ts_mcu_fit add_ts_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) @printf " UPDATE-FIT Top Swap: Microcode\n" diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc index 2f0c510..046f860 100644 --- a/src/security/intel/cbnt/Makefile.inc +++ b/src/security/intel/cbnt/Makefile.inc @@ -9,6 +9,7 @@ boot_policy_manifest.bin-type := raw boot_policy_manifest.bin-align := 0x10 +PHONY+=add_bpm_fit INTERMEDIATE+=add_bpm_fit add_bpm_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n boot_policy_manifest.bin -t 12 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< @@ -20,6 +21,7 @@ key_manifest.bin-type := raw key_manifest.bin-align := 0x10 +PHONY+=add_km_fit INTERMEDIATE+=add_km_fit add_km_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n key_manifest.bin -t 11 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index 77a5f69..dee4949 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -28,6 +28,7 @@ ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) +PHONY+=add_acm_fit INTERMEDIATE+=add_acm_fit add_acm_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) -t 2 \ @@ -42,6 +43,7 @@ ibb-files += bootblock +PHONY+=add_ibb_fit INTERMEDIATE+=add_ibb_fit add_ibb_fit: $(obj)/coreboot.pre $(IFITTOOL) $(foreach file, $(ibb-files), $(shell $(IFITTOOL) -f $< -a -n $(file) -t 7 \ diff --git a/src/soc/intel/common/block/fast_spi/Makefile.inc b/src/soc/intel/common/block/fast_spi/Makefile.inc index 79a2f97..d99c44f 100644 --- a/src/soc/intel/common/block/fast_spi/Makefile.inc +++ b/src/soc/intel/common/block/fast_spi/Makefile.inc @@ -46,6 +46,7 @@ done; \ if [ $$fail -eq 1 ]; then false; fi +PHONY+=check-fmap-16mib-crossing INTERMEDIATE+=check-fmap-16mib-crossing CBFSTOOL_ADD_CMD_OPTIONS += --ext-win-base $(CONFIG_EXT_BIOS_WIN_BASE) --ext-win-size $(CONFIG_EXT_BIOS_WIN_SIZE) diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 516cd4d..cc0a318 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -7,6 +7,7 @@ # image outside of CBFS ifeq ($(CONFIG_HAVE_IFD_BIN),y) +PHONY+=add_intel_firmware INTERMEDIATE+=add_intel_firmware else ifeq ($(CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED),y) files_added:: warn_intel_firmware -- To view, visit https://review.coreboot.org/c/coreboot/+/48897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I125e40204f3a9602ee5810d341ef40f9f50d045b Gerrit-Change-Number: 48897 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/crossgcc/.gitignore: Add cmake
by Arthur Heymans (Code Review) 08 Jan '21

08 Jan '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49115 ) Change subject: util/crossgcc/.gitignore: Add cmake ...................................................................... util/crossgcc/.gitignore: Add cmake Change-Id: I5ce346515f4468699396e214acfaa3b62f6d891d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/crossgcc/.gitignore 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/49115/1 diff --git a/util/crossgcc/.gitignore b/util/crossgcc/.gitignore index 0dfddd3..e6ff06c 100644 --- a/util/crossgcc/.gitignore +++ b/util/crossgcc/.gitignore @@ -1,6 +1,7 @@ acpica-unix-*/ binutils-*/ build-*BINUTILS/ +build-*CMAKE/ build-*EXPAT/ build-*GCC/ build-*GDB/ @@ -11,6 +12,7 @@ build-*PYTHON/ build-*LVM/ build-*IASL/ +cmake-*/ expat-*/ gcc-*/ gdb-*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/49115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ce346515f4468699396e214acfaa3b62f6d891d Gerrit-Change-Number: 49115 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: ec/system76/ec: Remove unused EC RAM fields
by Tim Crawford (Code Review) 08 Jan '21

08 Jan '21

Hello Jeremy Soller, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/49129 to review the following change. Change subject: ec/system76/ec: Remove unused EC RAM fields ...................................................................... ec/system76/ec: Remove unused EC RAM fields These fields were originally added for compatibility with the proprietary ITE EC firmware, but the System76 EC firmware does not use them. Take the opportunity to document most of the fields as well. Change-Id: I5581437c67ec67705ce16ba20254183a0261fd83 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/ec/system76/ec/acpi/ec_ram.asl 1 file changed, 44 insertions(+), 165 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/49129/1 diff --git a/src/ec/system76/ec/acpi/ec_ram.asl b/src/ec/system76/ec/acpi/ec_ram.asl index d5f97ed..6ef5454 100644 --- a/src/ec/system76/ec/acpi/ec_ram.asl +++ b/src/ec/system76/ec/acpi/ec_ram.asl @@ -3,173 +3,52 @@ OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) Field (ERAM, ByteAcc, Lock, Preserve) { - NMSG, 8, - SLED, 4, - Offset (0x02), - MODE, 1, - FAN0, 1, - TME0, 1, - TME1, 1, - FAN1, 1, - , 2, Offset (0x03), - LSTE, 1, - LSW0, 1, - LWKE, 1, - WAKF, 1, - , 2, - PWKE, 1, - MWKE, 1, - AC0, 8, - PSV, 8, - CRT, 8, - TMP, 8, - AC1, 8, - BBST, 8, - Offset (0x0B), - Offset (0x0C), - Offset (0x0D), - Offset (0x0E), - SLPT, 8, - SWEJ, 1, - SWCH, 1, + LSTE, 1, // Lid is open + , 1, + LWKE, 1, // Lid wake + , 5, + Offset (0x07), + TMP1, 8, // CPU temperature Offset (0x10), - ADP, 1, - AFLT, 1, - BAT0, 1, - BAT1, 1, - , 3, - PWOF, 1, - WFNO, 8, - BPU0, 32, - BDC0, 32, - BFC0, 32, - BTC0, 32, - BDV0, 32, - BST0, 32, - BPR0, 32, - BRC0, 32, - BPV0, 32, - BTP0, 16, - BRS0, 16, - BCW0, 32, - BCL0, 32, - BCG0, 32, - BG20, 32, - BMO0, 64, - BIF0, 64, - BSN0, 32, - BTY0, 64, - Offset (0x67), + ADP, 1, // AC adapter connected + , 1, + BAT0, 1, // Battery connected + , 5, + WFNO, 8, // Wake cause (not implemented) + Offset (0x16), + BDC0, 32, // Battery design capacity + BFC0, 32, // Battery full capacity + Offset (0x22), + BDV0, 32, // Battery design voltage + BST0, 32, // Battery status + BPR0, 32, // Battery current + BRC0, 32, // Battery remaining capacity + BPV0, 32, // Battery voltage + Offset (0x3A), + BCW0, 32, + BCL0, 32, Offset (0x68), - ECOS, 8, - LNXD, 8, - ECPS, 8, - Offset (0x6C), - BTMP, 16, - EVTN, 8, - Offset (0x72), - PRCL, 8, - PRC0, 8, - PRC1, 8, - PRCM, 8, - PRIN, 8, - PSTE, 8, - PCAD, 8, - PEWL, 8, - PWRL, 8, - PECD, 8, - PEHI, 8, - PECI, 8, - PEPL, 8, - PEPM, 8, - PWFC, 8, - PECC, 8, - PDT0, 8, - PDT1, 8, - PDT2, 8, - PDT3, 8, - PRFC, 8, - PRS0, 8, - PRS1, 8, - PRS2, 8, - PRS3, 8, - PRS4, 8, - PRCS, 8, - PEC0, 8, - PEC1, 8, - PEC2, 8, - PEC3, 8, - CMDR, 8, - CVRT, 8, - GTVR, 8, - FANT, 8, - SKNT, 8, - AMBT, 8, - MCRT, 8, - DIM0, 8, - DIM1, 8, - PMAX, 8, - PPDT, 8, - PECH, 8, - PMDT, 8, - TSD0, 8, - TSD1, 8, - TSD2, 8, - TSD3, 8, - CPUP, 16, - MCHP, 16, - SYSP, 16, - CPAP, 16, - MCAP, 16, - SYAP, 16, - CFSP, 16, - CPUE, 16, - Offset (0xC6), - Offset (0xC7), - VGAT, 8, - OEM1, 8, - OEM2, 8, - OEM3, 16, - OEM4, 8, - Offset (0xCE), - DUT1, 8, - DUT2, 8, - RPM1, 16, - RPM2, 16, - RPM4, 16, - Offset (0xD7), - DTHL, 8, - DTBP, 8, - AIRP, 8, - WINF, 8, - RINF, 8, - Offset (0xDD), - INF2, 8, - MUTE, 1, - Offset (0xE0), - RPM3, 16, - ECKS, 8, - Offset (0xE4), - , 4, - XTUF, 1, - EP12, 1, - Offset (0xE5), - INF3, 8, - Offset (0xE7), - GFOF, 8, - Offset (0xE9), - KPCR, 1, - Offset (0xEA), - Offset (0xF0), - PL1T, 16, - PL2T, 16, - TAUT, 8, + ECOS, 8, // Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver + Offset (0xC8), + OEM1, 8, + OEM2, 8, + OEM3, 16, + OEM4, 8, // Extra SCI data + Offset (0xCD), + TMP2, 8, // GPU temperature + DUT1, 8, // Fan 1 duty + DUT2, 8, // Fan 2 duty + RPM1, 16, // Fan 1 RPM + RPM2, 16, // Fan 2 RPM + Offset (0xD9), + AIRP, 8, // Airplane mode LED + WINF, 8, // Enable ACPI brightness controls Offset (0xF8), - FCMD, 8, - FDAT, 8, - FBUF, 8, - FBF1, 8, - FBF2, 8, - FBF3, 8 + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, + FBF3, 8, } -- To view, visit https://review.coreboot.org/c/coreboot/+/49129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5581437c67ec67705ce16ba20254183a0261fd83 Gerrit-Change-Number: 49129 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: cbfstool: Use flock() when accessing CBFS files
by Julius Werner (Code Review) 08 Jan '21

08 Jan '21

Hello Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/49190 to review the following change. Change subject: cbfstool: Use flock() when accessing CBFS files ...................................................................... cbfstool: Use flock() when accessing CBFS files Trying to do multiple operations on the same CBFS image at the same time likely leads to data corruption. For this reason, add BSD advisory file locking (flock()) to cbfstool (and ifittool which is using the same file I/O library), so that only one process will operate on the same file at the same time and the others will wait in line. This should help resolve parallel build issues with the INTERMEDIATE target on certain platforms. Unfortunately, some platforms use the INTERMEDIATE target to do a direct dd into the CBFS image. This should generally be discouraged and future platforms should aim to clearly deliminate regions that need to be written directly by platform scripts with custom FMAP sections, so that they can be written with `cbfstool write`. For the time being, update the legacy platforms that do this with explicit calls to the `flock` utility. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06 --- M src/ec/hp/kbc1126/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/intel/common/firmware/Makefile.inc M util/cbfstool/partitioned_file.c 5 files changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/49190/1 diff --git a/src/ec/hp/kbc1126/Makefile.inc b/src/ec/hp/kbc1126/Makefile.inc index 43e5d3f..d767bad 100644 --- a/src/ec/hp/kbc1126/Makefile.inc +++ b/src/ec/hp/kbc1126/Makefile.inc @@ -22,7 +22,7 @@ printf " Building kbc1126_ec_insert.\n" $(MAKE) -C util/kbc1126 printf " KBC1126 Inserting KBC1126 firmware blobs.\n" - $(KBC1126_EC_INSERT) $(obj)/coreboot.pre \ + flock $< $(KBC1126_EC_INSERT) $(obj)/coreboot.pre \ $(CONFIG_KBC1126_FW1_OFFSET) $(CONFIG_KBC1126_FW2_OFFSET) endif diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 969f512..2ad0730 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -172,7 +172,7 @@ add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ "$(STONEYRIDGE_FWM_ROM_POSITION)" - dd if=$(obj)/amdfw.rom \ + flock $< dd if=$(obj)/amdfw.rom \ of=$(obj)/coreboot.pre conv=notrunc bs=1 \ seek=$(STONEYRIDGE_FWM_ROM_POSITION) >/dev/null 2>&1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 215a5a1..5eac024 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -162,7 +162,7 @@ add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom printf " DD Adding AMD Firmware\n" - dd if=$(obj)/amdfw.rom \ + flock $< dd if=$(obj)/amdfw.rom \ of=$(obj)/coreboot.pre conv=notrunc bs=1 seek=131072 >/dev/null 2>&1 else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 516cd4d..588c663 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -35,7 +35,7 @@ endif add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(IFD_BIN_PATH) \ + flock $< dd if=$(IFD_BIN_PATH) \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 ifeq ($(CONFIG_VALIDATE_INTEL_DESCRIPTOR),y) $(objutil)/ifdtool/ifdtool \ diff --git a/util/cbfstool/partitioned_file.c b/util/cbfstool/partitioned_file.c index b6d4f1b..6e75600 100644 --- a/util/cbfstool/partitioned_file.c +++ b/util/cbfstool/partitioned_file.c @@ -8,6 +8,7 @@ #include <assert.h> #include <stdlib.h> #include <string.h> +#include <sys/file.h> struct partitioned_file { struct fmap *fmap; @@ -57,7 +58,7 @@ access_mode = write_access ? "rb+" : "rb"; file->stream = fopen(filename, access_mode); - if (!file->stream) { + if (!file->stream || flock(fileno(file->stream), LOCK_EX)) { perror(filename); partitioned_file_close(file); return NULL; @@ -78,7 +79,7 @@ } file->stream = fopen(filename, "wb"); - if (!file->stream) { + if (!file->stream || flock(fileno(file->stream), LOCK_EX)) { perror(filename); free(file); return NULL; @@ -268,6 +269,7 @@ file->fmap = NULL; buffer_delete(&file->buffer); if (file->stream) { + flock(fileno(file->stream), LOCK_UN); fclose(file->stream); file->stream = NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/49190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06 Gerrit-Change-Number: 49190 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: payloads/external/tianocore/Kconfig: elaborate help for TIANOCORE_BOO...
by Paul Menzel (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Felix Friedlander, Martin Roth, Stefan Reinauer. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49233 ) Change subject: payloads/external/tianocore/Kconfig: elaborate help for TIANOCORE_BOOTSPLASH_FILE ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49233/comment/1764cafe_0aecb8b4 PS1, Line 7: payloads/external/tianocore/Kconfig: elaborate help for TIANOCORE_BOOTSPLASH_FILE The prefix does not need to be the path (often it can be used though). Some suggestions: 1. payloads/tianocore/Kconfig: Extend help for bootsplash file 2. tianocore: Extend Kconfig help for bootsplash file 3. payloads/tianocore/Kconfig: Add detail on how bootsplash is used in OS File payloads/external/tianocore/Kconfig: https://review.coreboot.org/c/coreboot/+/49233/comment/ae76ac5a_3111c1bd PS1, Line 100: and will be displayed slightly above the centre of : the screen, I do not understand this. Do you mean, a log should be placed above the centre of the screen so the OS spinner and text does not overlay with it? https://review.coreboot.org/c/coreboot/+/49233/comment/9f607acd_d1914788 PS1, Line 102: than your display. If you have it handy, it’d be great if you put the URL to the specification here too. -- To view, visit https://review.coreboot.org/c/coreboot/+/49233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4c6666bb0e49369fe8fe2ae3dc12c023f668da0 Gerrit-Change-Number: 49233 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Friedlander <felix(a)ffetc.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Friedlander <felix(a)ffetc.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Jan 2021 08:02:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation
by Karthik Ramasubramanian (Code Review) 08 Jan '21

08 Jan '21

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49134 ) Change subject: mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation ...................................................................... mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation As part of acoustic noise mitigation calibration, we need to enable FastPkgCRampDisable upd along with slew rate = 1. This values has been derived based on noise calibration done. Please refer document 575216 for procedure. BUG=None BRANCH=dedede TEST=correct value has been programmed and slew rate measurement is correct on scope. Change-Id: Ie42c8ab647ff42fa043b6f717a9834f9b9c551f6 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49134 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Evan Green <evgreen(a)chromium.org> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Evan Green: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index e09dbe8..5959343 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -67,7 +67,8 @@ # Enable Acoustic noise mitigation and set slew rate to 1/4 # Rest of the parameters are 0 by default. register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate" = "1" + register "SlowSlewRate" = "SlewRateFastBy4" + register "FastPkgCRampDisable" = "1" device domain 0 on device pci 05.0 on # IPU - MIPI Camera -- To view, visit https://review.coreboot.org/c/coreboot/+/49134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie42c8ab647ff42fa043b6f717a9834f9b9c551f6 Gerrit-Change-Number: 49134 Gerrit-PatchSet: 8 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation
by Karthik Ramasubramanian (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Maulik V Vaghela. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49134 ) Change subject: mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49134/comment/2d2fe991_7ffb6809 PS5, Line 17: correct value has been programmed and slew rate measurement : is correct on scope. > I am waiting for ODM to confirm if this fixes the issue on their side as well. […] Ack. ODM informed that it may take a while for the acoustic lab to test the noise. The waveform is as expected. So will submit the CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/49134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie42c8ab647ff42fa043b6f717a9834f9b9c551f6 Gerrit-Change-Number: 49134 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 07:41:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Update acoustic noise related parameters
by Maulik V Vaghela (Code Review) 08 Jan '21

08 Jan '21

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49187 ) Change subject: soc/intel/jasperlake: Update acoustic noise related parameters ...................................................................... soc/intel/jasperlake: Update acoustic noise related parameters We need to fill Acoustic noise mitigation related UPDs only in case when acoustic noise mitigation is enabled. This will also clarify the user that they need to enable Acoustic noise mitigation while using this config in mainboard. BUG=None BRANCH=dedede TEST=Check that UPD values are getting filled correctly. Change-Id: I0cf4ccfced13b0d32b3d20713eace63e66945332 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/49187/1 diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index c03e9dd..0ccc461 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -237,12 +237,16 @@ config->PchPmPwrCycDur); /* Fill Acoustic noise mitigation related configuration */ - params->FastPkgCRampDisable[0] = config->FastPkgCRampDisable; - params->SlowSlewRate[0] = config->SlowSlewRate; + params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; - params->PreWake = config->PreWake; - params->RampUp = config->RampUp; - params->RampDown = config->RampDown; + + if (params->AcousticNoiseMitigation) { + params->FastPkgCRampDisable[0] = config->FastPkgCRampDisable; + params->SlowSlewRate[0] = config->SlowSlewRate; + params->PreWake = config->PreWake; + params->RampUp = config->RampUp; + params->RampDown = config->RampDown; + } /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); -- To view, visit https://review.coreboot.org/c/coreboot/+/49187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cf4ccfced13b0d32b3d20713eace63e66945332 Gerrit-Change-Number: 49187 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/sx9324: Add more register
by Stanley Wu (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Henry Sun, Karthik Ramasubramanian. Stanley Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49220 ) Change subject: drivers/i2c/sx9324: Add more register ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49220/comment/d9c65eea_59a5b782 PS1, Line 9: Export registers that driver is looking for. > Can you please mention what registers are being added and what is the purpose of those registers. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cee84a5658fecf55d2d8b8621879588ffe0158d Gerrit-Change-Number: 49220 Gerrit-PatchSet: 3 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 07:25:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit January 2021