coreboot-gerrit January 2021

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Change in coreboot[master]: util/testing: remove genprof target
by Felix Singer (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Martin Roth, Felix Held. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49226 ) Change subject: util/testing: remove genprof target ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I420b5c43e2d97373a8e665f457463a06e16ecfb9 Gerrit-Change-Number: 49226 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Jan 2021 06:06:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magolor: Remove the unused touch controller
by Karthik Ramasubramanian (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Ren Kuo, Tim Chen. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49221 ) Change subject: mb/google/dedede/var/magolor: Remove the unused touch controller ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a01666bc1e353e21ddf961a0eb721a0cb4013db Gerrit-Change-Number: 49221 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 05:36:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Fix tsc_freq_mhz() on some platforms
by Stefan Reinauer (Code Review) 08 Jan '21

08 Jan '21

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49232 ) Change subject: Fix tsc_freq_mhz() on some platforms ...................................................................... Fix tsc_freq_mhz() on some platforms On platforms where cpuid_get_max_func() is < 0x15 the guard that was added to get_freq_from_cpuid16h() does not provide any protection from producing the wrong result. Instead, the code returned 0 which leads to silent crashes in the call chain. Utilize CONFIG_CPU_BCLK_MHZ to prevent this from happening. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Ic42a057945a48d8bf0641d1418160906cd15a991 --- M src/soc/intel/common/block/timer/timer.c 1 file changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/49232/1 diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c index ab41149..e7920ee 100644 --- a/src/soc/intel/common/block/timer/timer.c +++ b/src/soc/intel/common/block/timer/timer.c @@ -93,9 +93,12 @@ unsigned long tsc_freq_mhz(void) { - unsigned long tsc_freq; + int max_func = cpuid_get_max_func(); + unsigned long tsc_freq = 0; + msr_t platform_info; - tsc_freq = calculate_tsc_freq_from_core_crystal(); + if (max_func >= 0x15) + tsc_freq = calculate_tsc_freq_from_core_crystal(); if (tsc_freq) return tsc_freq; @@ -104,5 +107,9 @@ * Some Intel SoCs like Skylake, Kabylake and Cometlake don't report * the crystal clock, in that case return bus frequency using CPUID.16h */ - return get_freq_from_cpuid16h(); + if (max_func >= 0x16) + return get_freq_from_cpuid16h(); + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return CONFIG_CPU_BCLK_MHZ * ((platform_info.lo >> 8) & 0xff); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic42a057945a48d8bf0641d1418160906cd15a991 Gerrit-Change-Number: 49232 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/autoport: Rename to mainboard_fill_gnvs()
by Kyösti Mälkki (Code Review) 08 Jan '21

08 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49231 ) Change subject: util/autoport: Rename to mainboard_fill_gnvs() ...................................................................... util/autoport: Rename to mainboard_fill_gnvs() Change-Id: Ia8d7083ca2f21abbb5f184c1b55dcf1bf047a7be Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M util/autoport/bd82x6x.go M util/autoport/readme.md 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/49231/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 5d943e4..e2a84e4 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -359,10 +359,11 @@ defer gnvs.Close() Add_gpl(gnvs) - gnvs.WriteString(`#include <southbridge/intel/bd82x6x/nvs.h> + gnvs.WriteString(`#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> /* FIXME: check this function. */ -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default. */ gnvs->lids = 1; diff --git a/util/autoport/readme.md b/util/autoport/readme.md index bfaaef6..f2b2697 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -335,7 +335,7 @@ ## GNVS -`acpi_create_gnvs` sets values in GNVS, which then ACPI makes use of for +`mainboard_fill_gnvs` sets values in GNVS, which then ACPI makes use of for various power-related functions. Normally, there is no need to modify it on laptops (desktops have no "lid"!) but it makes sense to proofread it. -- To view, visit https://review.coreboot.org/c/coreboot/+/49231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8d7083ca2f21abbb5f184c1b55dcf1bf047a7be Gerrit-Change-Number: 49231 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/magolor: Remove the unused touch controller
by Ren Kuo (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Tim Chen, Karthik Ramasubramanian. Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49221 ) Change subject: mb/google/dedede/var/magolor: Remove the unused touch controller ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49221/comment/9a29fca0_e61b9072 PS1, Line 7: mb/google/dedede/var/magolor: remove the unused touch controller > Nit: Always start the sentence with a capital letter. Done https://review.coreboot.org/c/coreboot/+/49221/comment/3fa6fc8a_5b3e3cfc PS1, Line 11: BUG=None > BRANCH=dedede Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a01666bc1e353e21ddf961a0eb721a0cb4013db Gerrit-Change-Number: 49221 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 05:02:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magolor: Remove the unused touch controller
by Ren Kuo (Code Review) 08 Jan '21

08 Jan '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Ren Kuo, Tim Chen. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Henry Sun, Tim Chen, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49221 to look at the new patch set (#2). Change subject: mb/google/dedede/var/magolor: Remove the unused touch controller ...................................................................... mb/google/dedede/var/magolor: Remove the unused touch controller Remove unused touch controller - Goodix BUG=None BRANCH=dedede TEST=build firmware Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: I2a01666bc1e353e21ddf961a0eb721a0cb4013db --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49221/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a01666bc1e353e21ddf961a0eb721a0cb4013db Gerrit-Change-Number: 49221 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Tim Crawford (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Felix Singer, Nico Huber, Jeremy Soller. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49104/comment/b68b2fe9_89c79092 PS5, Line 14: the TigerLake FSP Integration Guide. > I couldn't find it, can you be more specific? […] I will clarify the it to be the table override behavior in the message, and reference the section in the doc. https://review.coreboot.org/c/coreboot/+/49104/comment/4b2b1e6d_3ee1e368 PS5, Line 23: Tested by checking lspci output on System76 galp3-c, oryp5, oryp6. > I can't find any of them in the tree. […] These are WHL (galp3-c), CFL (oryp5, CB:47892), and CML (oryp6, CB:47768). I will specify the FSP in the message. File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/3ad9a3f4_319b49d2 PS5, Line 552: 0 > This looks like a valid address to me: offset 0 of PCI 0:00.0, or did I […] You're right. The PCI ID database doesn't list anything using it, but it does appear to be valid. https://review.coreboot.org/c/coreboot/+/49104/comment/e5fb590d_e11cf0e4 PS5, Line 561: dev = pcidev_path_on_root(PCH_DEVFN_XHCI); : if (dev) : pci_dev_set_subsystem(dev, dev->subsystem_vendor, : dev->subsystem_device); : : dev = pcidev_path_on_root(PCH_DEVFN_HDA); : if (dev) : pci_dev_set_subsystem(dev, dev->subsystem_vendor, : dev->subsystem_device); > Alternatively to a dummy entry, why not move this into the table? Yes. Based on your other comments, I believe this is the better option. Moving them into the table would comply with what little documentation there is instead of relying on unknown behavior of the FSP. -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 02:37:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
by Karthik Ramasubramanian (Code Review) 07 Jan '21

07 Jan '21

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49012 ) Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification ...................................................................... soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification USBSUSPGQDIS is a disqualifier bit which will allow platform to enter s0ix even if USB2 PHY SUS is not power gated. Disabling this bit will ensure that USB2 PHY SUS is power gated before entering s0ix. BUG=b:175767084 BRANCH=dedede TEST=s0ix works on drawcia and USB wake from s0ix works fine. Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49012 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Evan Green <evgreen(a)chromium.org> --- M src/soc/intel/jasperlake/finalize.c M src/soc/intel/jasperlake/include/soc/pmc.h 2 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, but someone else must approve Evan Green: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index d879db9..8219f0c 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -40,6 +40,8 @@ static void pch_finalize(void) { + uint32_t reg32; + uint8_t *pmcbase; config_t *config; /* TCO Lock down */ @@ -62,6 +64,17 @@ if (config->PmTimerDisabled) pmc_disable_acpi_timer(); + pmcbase = pmc_mmio_regs(); + if (config->s0ix_enable) { + /* + * Enable USBSUSPGQDIS qualification to ensure USB2 PHY SUS is power gated + * before entering s0ix. + */ + reg32 = read32(pmcbase + CPPMVRIC3); + reg32 &= ~USBSUSPGQDIS; + write32(pmcbase + CPPMVRIC3, reg32); + } + pch_handle_sideband(config); pmc_clear_pmcon_sts(); diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index 34172f8..e65e884 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -122,6 +122,9 @@ #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) +#define CPPMVRIC3 0x1E4C +#define USBSUSPGQDIS (1 << 15) + #define IRQ_REG ACTL #define SCI_IRQ_ADJUST 0 #define ACTL 0x1BD8 -- To view, visit https://review.coreboot.org/c/coreboot/+/49012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Gerrit-Change-Number: 49012 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
by Karthik Ramasubramanian (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Krishna P Bhat D. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 ) Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Since this change is needed urgently to unblock the milestone, submitting it now. The change applies only to jasperlake SoC and hence Dedede & JSLRVP MBs only. -- To view, visit https://review.coreboot.org/c/coreboot/+/49012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Gerrit-Change-Number: 49012 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 01:51:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation
by Evan Green (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Maulik V Vaghela. Evan Green has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49134 ) Change subject: mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie42c8ab647ff42fa043b6f717a9834f9b9c551f6 Gerrit-Change-Number: 49134 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 01:34:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2021