coreboot-gerrit January 2021

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Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
by Karthik Ramasubramanian (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Krishna P Bhat D. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 ) Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Since this change is needed urgently to unblock the milestone, submitting it now. The change applies only to jasperlake SoC and hence Dedede & JSLRVP MBs only. -- To view, visit https://review.coreboot.org/c/coreboot/+/49012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Gerrit-Change-Number: 49012 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 01:51:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation
by Evan Green (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Maulik V Vaghela. Evan Green has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49134 ) Change subject: mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie42c8ab647ff42fa043b6f717a9834f9b9c551f6 Gerrit-Change-Number: 49134 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 01:34:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
by Evan Green (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Krishna P Bhat D. Evan Green has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 ) Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: I tested a firmware built by Karthik with this change and was able to pass 5 iterations of firmware_ECWakeSource. -- To view, visit https://review.coreboot.org/c/coreboot/+/49012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Gerrit-Change-Number: 49012 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 01:31:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Nico Huber (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Felix Singer, Tim Crawford, Jeremy Soller. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49104/comment/c77056a5_a3894706 PS5, Line 14: the TigerLake FSP Integration Guide. I couldn't find it, can you be more specific? (I did find example code, but nothing about the behavior when using a dummy, all-zero entry.) https://review.coreboot.org/c/coreboot/+/49104/comment/6f419d62_0f7660e2 PS5, Line 23: Tested by checking lspci output on System76 galp3-c, oryp5, oryp6. I can't find any of them in the tree. Which FSP do they use? File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/67e7ddb7_ae0581c1 PS5, Line 552: 0 This looks like a valid address to me: offset 0 of PCI 0:00.0, or did I miss something? If that's the case, FSP would try to write the VID/DID pair of that device which seems like a crude hack. Shouldn't we use an address of a known, non-existent device? https://review.coreboot.org/c/coreboot/+/49104/comment/32ace12a_142ae28f PS5, Line 561: dev = pcidev_path_on_root(PCH_DEVFN_XHCI); : if (dev) : pci_dev_set_subsystem(dev, dev->subsystem_vendor, : dev->subsystem_device); : : dev = pcidev_path_on_root(PCH_DEVFN_HDA); : if (dev) : pci_dev_set_subsystem(dev, dev->subsystem_vendor, : dev->subsystem_device); Alternatively to a dummy entry, why not move this into the table? -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Fri, 08 Jan 2021 00:29:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in em100[master]: for ron
by ron minnich (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Stefan Reinauer. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/em100/+/49230 ) Change subject: for ron ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: it may not look like much, but it's got it where it counts. -- To view, visit https://review.coreboot.org/c/em100/+/49230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ib92e5a759fce2e627c074ae1453fae93a0268003 Gerrit-Change-Number: 49230 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Jan 2021 23:34:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in em100[master]: for ron
by Stefan Reinauer (Code Review) 07 Jan '21

07 Jan '21

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/49230 ) Change subject: for ron ...................................................................... for ron Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Ib92e5a759fce2e627c074ae1453fae93a0268003 --- M trace.c 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/30/49230/1 diff --git a/trace.c b/trace.c index e1f065f..90dfd93 100644 --- a/trace.c +++ b/trace.c @@ -13,6 +13,7 @@ #include <stdio.h> #include <string.h> +#include <ctype.h> #include "em100.h" int trace_brief = 0; @@ -284,7 +285,7 @@ j = MAX_TRACE_BLOCKLENGTH; } - if (trace_brief) { + if (trace_brief == 2) { if (start_timestamp) start_timestamp = 0; @@ -298,6 +299,19 @@ } else printf("0x%02x (%s)\n", spi_command, spi_cmd_vals->cmd_name); + } else if (trace_brief == 1) { // memory read console + if (start_timestamp) + start_timestamp = 0; + + if (spi_cmd_vals->address_type != ADDR_NONE && spi_cmd_vals->address_type != ADDR_NO_OFF_3B) { + if ((address >> 16) == 0xc0) { + uint8_t c = (uint8_t)(address>>6); + if (isascii(c) || c==10) + printf("%c", c); + else + printf("\\%o", c); + } + } } else { printf("\nTime: %06lld.%08lld", (timestamp - start_timestamp) / -- To view, visit https://review.coreboot.org/c/em100/+/49230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ib92e5a759fce2e627c074ae1453fae93a0268003 Gerrit-Change-Number: 49230 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
by Karthik Ramasubramanian (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Krishna P Bhat D. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 ) Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49012/comment/ea64a377_ef5ed192 PS4, Line 15: s0ix works on drawcia and USB wake from s0ix works fine. > We have not checked with USB3 HID device, could not get hold of one. Ack. We can go ahead with this change for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/49012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Gerrit-Change-Number: 49012 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 07 Jan 2021 22:48:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
by Karthik Ramasubramanian (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Krishna P Bhat D. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 ) Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Gerrit-Change-Number: 49012 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 07 Jan 2021 22:46:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ACPI: Remove ACPI_NO_SMI_GNVS
by Kyösti Mälkki (Code Review) 07 Jan '21

07 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49127 ) Change subject: ACPI: Remove ACPI_NO_SMI_GNVS ...................................................................... ACPI: Remove ACPI_NO_SMI_GNVS This was used as a guard to not raise SMI with APM_CNT_GNVS_UPDATE. The handler has been removed now completely. Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/Kconfig M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/xeon_sp/Kconfig 6 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/49127/1 diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 07008db..11ef12a3 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -24,9 +24,6 @@ Provide common definitions for Intel hardware PM1_CNT register sleep values. -config ACPI_NO_SMI_GNVS - bool - config ACPI_NO_PCAT_8259 bool help diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 1ccfa5d..b144fc1 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -14,7 +14,6 @@ select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select SSE2 - select ACPI_NO_SMI_GNVS if CPU_AMD_AGESA diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index dff896f..d3a94a8c 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -13,7 +13,6 @@ select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select SSE2 - select ACPI_NO_SMI_GNVS if CPU_AMD_PI diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e9930e9..4d31267 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -57,7 +57,6 @@ select UDK_2017_BINDING select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS - select ACPI_NO_SMI_GNVS config FSP_M_FILE string "FSP-M (memory init) binary path and filename" diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b95dbf4..7d2ad21 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -10,7 +10,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_AMD_HARDWARE_SLEEP_VALUES - select ACPI_NO_SMI_GNVS select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select COLLECT_TIMESTAMPS_NO_TSC diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 3b95c70..a8cecc5 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -36,7 +36,6 @@ select POSTCAR_STAGE select IOAPIC select PARALLEL_MP - select ACPI_NO_SMI_GNVS select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU -- To view, visit https://review.coreboot.org/c/coreboot/+/49127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db Gerrit-Change-Number: 49127 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
by Furquan Shaikh (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Krishna P Bhat D. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 ) Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Patchset: PS5: LGTM. I will let Karthik +2 this. -- To view, visit https://review.coreboot.org/c/coreboot/+/49012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Gerrit-Change-Number: 49012 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 07 Jan 2021 20:56:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2021