coreboot-gerrit January 2021

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Tim Crawford (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Felix Singer, Jeremy Soller, Angel Pons. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/19c8bdd6_bf56f1d1 PS2, Line 552: /* Program XHCI SSID/SVID before FSP silicon init */ : dev = pcidev_path_on_root(PCH_DEVFN_XHCI); : if (!dev->subsystem_vendor || !dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : } : : /* Program HDAudio SSID/SVID before FSP silicon init */ : dev = pcidev_path_on_root(PCH_DEVFN_HDA); : if (!dev->subsystem_vendor || !dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : } > We know that the SVID/SSID registers are write-once, and FSP writes to them before coreboot does, so […] *Most* are RW/O. These two specifically are RW/L. They can be written multiple times, and will get locked regardless of writing to them. coreboot is still writing them after SiliconInit in pci_dev_enable_resources(). That has not change, including attempting to write these two devices' SSIDs. But the RW/O work now because the FSP is not writing them. So specifically for these RW/L registers, they must be written before the lock happens. -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Jan 2021 17:34:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Don't run SCHECK on CBnT
by Arthur Heymans (Code Review) 07 Jan '21

07 Jan '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49164 ) Change subject: security/intel/txt: Don't run SCHECK on CBnT ...................................................................... security/intel/txt: Don't run SCHECK on CBnT This functionality only exists on legacy TXT. Change-Id: I4206ba65fafbe3d4dda626a8807e415ce6d64633 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/txt/ramstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/49164/1 diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index cbc3a41..3401aef 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -171,7 +171,7 @@ } int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { + if (!s3resume && !CONFIG(INTEL_CBNT_SUPPORT)) { printk(BIOS_INFO, "TEE-TXT: Scheck...\n"); if (intel_txt_run_bios_acm(ACMINPUT_SCHECK) < 0) { printk(BIOS_ERR, "TEE-TXT: Error calling BIOS ACM.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/49164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4206ba65fafbe3d4dda626a8807e415ce6d64633 Gerrit-Change-Number: 49164 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/cbfstool/ifittool: Add an option to just print the FIT table
by Arthur Heymans (Code Review) 07 Jan '21

07 Jan '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49225 ) Change subject: util/cbfstool/ifittool: Add an option to just print the FIT table ...................................................................... util/cbfstool/ifittool: Add an option to just print the FIT table Add a coreboot-agnostic option '-P|--print-fit' to just print a FIT table. TESTED: can print the FIT table of both a coreboot and an UEFI image. Change-Id: I341c8e7ad6efaeacceaa403534310fa4cf345b5f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/ifittool.c 1 file changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/49225/1 diff --git a/util/cbfstool/ifittool.c b/util/cbfstool/ifittool.c index 7e99d4f..b6d4d8e 100644 --- a/util/cbfstool/ifittool.c +++ b/util/cbfstool/ifittool.c @@ -15,7 +15,7 @@ /* Global variables */ partitioned_file_t *image_file; -static const char *optstring = "H:j:f:r:d:t:n:s:cAaDvh?"; +static const char *optstring = "H:j:f:r:d:t:n:s:cAaDvhP?"; static struct option long_options[] = { {"file", required_argument, 0, 'f' }, {"region", required_argument, 0, 'r' }, @@ -28,6 +28,7 @@ {"max-table-size", required_argument, 0, 's' }, {"topswap-size", required_argument, 0, 'j' }, {"dump", no_argument, 0, 'D' }, + {"print-fit", no_argument, 0, 'P' }, {"verbose", no_argument, 0, 'v' }, {"help", no_argument, 0, 'h' }, {"header-offset", required_argument, 0, 'H' }, @@ -50,6 +51,7 @@ "\t\t-H|--header-offset : Do not search for header, use this offset\n" "\t\t-v|--verbose : Be verbose\n" "\t\t-D|--dump : Dump FIT table (at end of operation)\n" + "\t\t-P|--print-fit : Print the FIT table of any image (only needs the file argument)\n" "\t\t-c|--clear-table : Remove all existing entries (do not update)\n" "\t\t-j|--topswap-size : Use second FIT table if non zero\n" "\tREQUIRED ARGUMENTS:\n" @@ -128,7 +130,8 @@ ADD_CBFS_OP, ADD_REGI_OP, ADD_ADDR_OP, - DEL_OP + DEL_OP, + PRINT_OP }; int main(int argc, char *argv[]) @@ -206,6 +209,14 @@ case 'D': dump = true; break; + case 'P': + if (op != NO_OP) { + ERROR("specified multiple actions at once\n"); + usage(argv[0]); + return 1; + } + op = PRINT_OP; + break; case 'f': input_file = optarg; break; @@ -273,6 +284,20 @@ return 1; } } + if (op == PRINT_OP) { + struct buffer input_buffer; + buffer_from_file(&input_buffer, input_file); + + struct fit_table *fit = + fit_get_table(&input_buffer, convert_to_from_top_aligned, topswap_size); + + if (fit_dump(fit)) { + buffer_delete(&input_buffer); + return 1; + } + buffer_delete(&input_buffer); + return 0; + } if (!region_name) { ERROR("Region not given\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/49225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I341c8e7ad6efaeacceaa403534310fa4cf345b5f Gerrit-Change-Number: 49225 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/magolor: remove the unused touch controller
by Karthik Ramasubramanian (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Ren Kuo, Tim Chen. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49221 ) Change subject: mb/google/dedede/var/magolor: remove the unused touch controller ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49221/comment/53799b56_ad5731b6 PS1, Line 7: mb/google/dedede/var/magolor: remove the unused touch controller Nit: Always start the sentence with a capital letter. https://review.coreboot.org/c/coreboot/+/49221/comment/8fcd1f9a_53116f44 PS1, Line 11: BUG=None BRANCH=dedede -- To view, visit https://review.coreboot.org/c/coreboot/+/49221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a01666bc1e353e21ddf961a0eb721a0cb4013db Gerrit-Change-Number: 49221 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 07 Jan 2021 16:23:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/sx9324: Add more register
by Karthik Ramasubramanian (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Henry Sun, Stanley Wu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49220 ) Change subject: drivers/i2c/sx9324: Add more register ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49220/comment/4ade79ac_3331c95e PS1, Line 9: Export registers that driver is looking for. Can you please mention what registers are being added and what is the purpose of those registers. -- To view, visit https://review.coreboot.org/c/coreboot/+/49220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cee84a5658fecf55d2d8b8621879588ffe0158d Gerrit-Change-Number: 49220 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Thu, 07 Jan 2021 16:21:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation
by Karthik Ramasubramanian (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Maulik V Vaghela. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49134 ) Change subject: mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie42c8ab647ff42fa043b6f717a9834f9b9c551f6 Gerrit-Change-Number: 49134 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Thu, 07 Jan 2021 16:19:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amd_blobs: Advance pointer for picasso FSP 0x25
by Raul Rangel (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Marshall Dawson. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49223 ) Change subject: amd_blobs: Advance pointer for picasso FSP 0x25 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aa5f353432cd8f79005153a06ac35c1e654f6f1 Gerrit-Change-Number: 49223 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Jan 2021 16:09:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Enable wake from USB in S4
by Angel Pons (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49224 ) Change subject: soc/intel/cannonlake: Enable wake from USB in S4 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bb266e70ee6b4eb8922671b7d0078db0d29a1da Gerrit-Change-Number: 49224 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 07 Jan 2021 16:00:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Angel Pons (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Felix Singer, Tim Crawford, Jeremy Soller. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 3: (2 comments) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/25daba99_d7f99099 PS2, Line 552: /* Program XHCI SSID/SVID before FSP silicon init */ : dev = pcidev_path_on_root(PCH_DEVFN_XHCI); : if (!dev->subsystem_vendor || !dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : } : : /* Program HDAudio SSID/SVID before FSP silicon init */ : dev = pcidev_path_on_root(PCH_DEVFN_HDA); : if (!dev->subsystem_vendor || !dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : } > From what Jeremy has told me, the registers are locked during FSP-S. […] We know that the SVID/SSID registers are write-once, and FSP writes to them before coreboot does, so they end up with undesired values. This patch does two things: 1. sets some FSP UPDs related to SVID/SSID programming 2. programs the SVID/SSID registers in coreboot before running FSP The problem I see is that these two things are mutually exclusive, so one of them is unnecessary. Either FSP or coreboot does the first write to a SVID/SSID register and makes it become read-only. Is there a reason to change the FSP UPDs when coreboot programs the SVID/SSID registers? File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/comment/d06f3cf8_89d8ff08 PS3, Line 555: if (dev->subsystem_vendor && dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } This logic is already implemented in `pci_dev_set_subsystem` -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Thu, 07 Jan 2021 15:59:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Enable wake from USB in S4
by Arthur Heymans (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49224 ) Change subject: soc/intel/cannonlake: Enable wake from USB in S4 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bb266e70ee6b4eb8922671b7d0078db0d29a1da Gerrit-Change-Number: 49224 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 07 Jan 2021 15:59:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2021