coreboot-gerrit May 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/jasperlake: Add Sata related UPDs configuration
by Furquan Shaikh (Code Review) 07 May '20

07 May '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41029 ) Change subject: soc/intel/jasperlake: Add Sata related UPDs configuration ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/c/coreboot/+/41029/6/src/soc/intel/jasperlake/f… File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/41029/6/src/soc/intel/jasperlake/f… PS6, Line 139: dev->enabled > changed. […] Now that SataEnable is dropped here, it should also be dropped from chip.h? https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/jasperlake… https://review.coreboot.org/c/coreboot/+/41029/6/src/soc/intel/jasperlake/f… PS6, Line 140: SataEnable > added all upds. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/41029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f Gerrit-Change-Number: 41029 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 May 2020 16:37:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/external/Makefile.inc: Pass hardware IRQ option to SeaBIOS M...
by Michał Żygowski (Code Review) 07 May '20

07 May '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41147 ) Change subject: payloads/external/Makefile.inc: Pass hardware IRQ option to SeaBIOS Makefile ...................................................................... payloads/external/Makefile.inc: Pass hardware IRQ option to SeaBIOS Makefile The hardware IRQ option was not passed to SeaBIOS Makefile and resulted in HARDWARE_IRQ being permanently disabled regardless of Kconfig selection in coreboot. On platforms that need the hardware IRQ it caused hangs at boot menu or iPXE prompts. TEST=enter SeaBIOS boot menu on Libretrend LT1000 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Iafcfd743177bbcd1ee23e227c74dd8268c4c23c6 --- M payloads/external/Makefile.inc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/41147/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 7319a11..5274581 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -102,7 +102,8 @@ CONFIG_SEABIOS_DEBUG_LEVEL=$(CONFIG_SEABIOS_DEBUG_LEVEL) \ CONFIG_DRIVERS_UART_8250MEM_32=$(CONFIG_DRIVERS_UART_8250MEM_32) \ CONFIG_ENABLE_HSUART=$(CONFIG_ENABLE_HSUART) \ - CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS) + CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS) \ + CONFIG_SEABIOS_HARDWARE_IRQ=$(CONFIG_SEABIOS_HARDWARE_IRQ) payloads/external/SeaBIOS/seabios/out/vgabios.bin: payloads/external/SeaBIOS/seabios/out/bios.bin.elf payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out/bios.bin.elf -- To view, visit https://review.coreboot.org/c/coreboot/+/41147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafcfd743177bbcd1ee23e227c74dd8268c4c23c6 Gerrit-Change-Number: 41147 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Enable EARLY_EC_SYNC
by Tim Wawrzynczak (Code Review) 07 May '20

07 May '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41078 ) Change subject: mb/google/volteer: Enable EARLY_EC_SYNC ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/41078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb97c1d57220f7fd74131a5aee450b1ab4b1c982 Gerrit-Change-Number: 41078 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 May 2020 16:15:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Add LPC and ESPI buses
by Raul Rangel (Code Review) 07 May '20

07 May '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41099 ) Change subject: util/sconfig: Add LPC and ESPI buses ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/41099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 Gerrit-Change-Number: 41099 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 May 2020 16:11:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/x9scl/early_init: Remove unused includes
by HAOUAS Elyes (Code Review) 07 May '20

07 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40827 ) Change subject: mb/x9scl/early_init: Remove unused includes ...................................................................... mb/x9scl/early_init: Remove unused includes Change-Id: I455a43ab6c4931a4fb1f717a65013b6b7cefb777 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/supermicro/x9scl/early_init.c 1 file changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/40827/1 diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c index b4a39fe..a2f89e7 100644 --- a/src/mainboard/supermicro/x9scl/early_init.c +++ b/src/mainboard/supermicro/x9scl/early_init.c @@ -1,25 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* FIXME: Check if all includes are needed. */ - #include <stdint.h> -#include <string.h> -#include <timestamp.h> -#include <arch/byteorder.h> -#include <device/mmio.h> #include <device/pci_ops.h> #include <device/pnp_def.h> #include <device/pnp_ops.h> -#include <console/console.h> #include <bootblock_common.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> #include <superio/nuvoton/wpcm450/wpcm450.h> + #include "x9scl.h" #define SERIAL_DEV PNP_DEV(X9SCL_NCT6776_PNP_BASE, NCT6776_SP1) -- To view, visit https://review.coreboot.org/c/coreboot/+/40827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I455a43ab6c4931a4fb1f717a65013b6b7cefb777 Gerrit-Change-Number: 40827 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/n141cu: Add new Comet Lake mainboard
by Felix Singer (Code Review) 07 May '20

07 May '20

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Change in coreboot[master]: soc/intel/tigerlake: Add PMC to platform ACPI name entry
by John Zhao (Code Review) 07 May '20

07 May '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41064 ) Change subject: soc/intel/tigerlake: Add PMC to platform ACPI name entry ...................................................................... soc/intel/tigerlake: Add PMC to platform ACPI name entry PMC device name string "PMC" is added to platform soc_acpi_name() for pmc driver. BUG=b:151646486 TEST=Built and booted to kernel successfully. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ida7fc7e2340f2a809464ca66fd1922f3229e2e18 --- M src/soc/intel/tigerlake/chip.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/41064/1 diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 073c8d2..b806dbb 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -80,6 +80,7 @@ case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PMC: return "PMC"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; case PCH_DEVFN_UART2: return "UAR2"; -- To view, visit https://review.coreboot.org/c/coreboot/+/41064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida7fc7e2340f2a809464ca66fd1922f3229e2e18 Gerrit-Change-Number: 41064 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/n141cu: Add new Comet Lake mainboard
by Felix Singer (Code Review) 07 May '20

07 May '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40581 ) Change subject: mb/clevo/n141cu: Add new Comet Lake mainboard ...................................................................... Patch Set 32: (6 comments) https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/Kconfig: https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… PS31, Line 38: default "clevo/cml-u" : : config VARIANT_DIR : default "n141cu" : : config MAINBOARD_FAMILY : default "Comet Lake" : > hmm, are there multiple latops that are expected to be mostly idenatical or at least very similar? Yes, the Clevo notebooks have a very similar layout and therefore we can sum up them by platform. https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/board_info.txt: https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… PS31, Line 2: Board name: cml-u > that's not the board/laptop name, is it? Removed that and created board_info.txt in the variants folder. https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/ramstage.c: https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… PS31, Line 11: Make M.2 port configurable (SATA <> > It usually boils down to configuring a GPIO properly Correct. Depending on the function you want, you just need to set a different GPIO configuration. https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/variants/n141cu/devicetree.cb: https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… PS31, Line 35: subsystemid 0x1558 0x1403 > you can inherit that Done https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… PS31, Line 169: register "deep_s3_enable_ac" = "0" > you can drop the 0 values, since they are default Done https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/variants/n141cu/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… PS31, Line 13: P1, : DP2, : DP3, : HDMI1, : HDMI2, : HDMI3, : eDP, : others > so many ports? libgfxinit doesn't have support for this platform yet and at the moment this file is unused. Therefore I am not able to test the ports. Nevertheless I added all necessary so that once libgfxinit has support for it one just needs to remove the # in the Kconfig. -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 32 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner Gerrit-Comment-Date: Thu, 07 May 2020 13:10:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/n141cu: Add new Comet Lake mainboard
by Felix Singer (Code Review) 07 May '20

07 May '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40581 to look at the new patch set (#32). Change subject: mb/clevo/n141cu: Add new Comet Lake mainboard ...................................................................... mb/clevo/n141cu: Add new Comet Lake mainboard Add a new mainboard with the following specs: - Intel i5-10210U (Comet Lake) - Intel UHD graphics - Intel HD audio - 1x Ethernet 1Gbit/s - 1x SATA3 - 1x M.2 slot x4 (PCIe/SATA) - 1x M.2 slot x1 (WLAN/BT) - 1x 3G/LTE - USB2/3 - Thunderbolt - HDMI, mDP - CCD camera + mic - SD card reader - TPM2 SLB9670 The ACPI code has been taken from System76 CML-U mainboard series. Tested: - Clevo N141CU / TUXEDO InfinityBook Pro 14 v5 - SeaBIOS and TianoCore - vboot with RO, RO+A, RO+A+B - Booted Arch Linux - Linux 5.6.10 - Linux LTS 5.4.38 What works / What works not: - WLAN/BT does not work, but also not with vendor firmware. - Everything else works. Todos: - Missing libgfxinit support, since it does not support the Comet Lake platform yet. - Different configuration switches mentioned in ramstage.c. Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 --- M MAINTAINERS A src/mainboard/clevo/Kconfig A src/mainboard/clevo/Kconfig.name A src/mainboard/clevo/cml-u/Kconfig A src/mainboard/clevo/cml-u/Kconfig.name A src/mainboard/clevo/cml-u/Makefile.inc A src/mainboard/clevo/cml-u/acpi/ac.asl A src/mainboard/clevo/cml-u/acpi/battery.asl A src/mainboard/clevo/cml-u/acpi/buttons.asl A src/mainboard/clevo/cml-u/acpi/ec.asl A src/mainboard/clevo/cml-u/acpi/ec_ram.asl A src/mainboard/clevo/cml-u/acpi/gpe.asl A src/mainboard/clevo/cml-u/acpi/hid.asl A src/mainboard/clevo/cml-u/acpi/keyboard.asl A src/mainboard/clevo/cml-u/acpi/lid.asl A src/mainboard/clevo/cml-u/acpi/mainboard.asl A src/mainboard/clevo/cml-u/acpi/sleep.asl A src/mainboard/clevo/cml-u/acpi/tbt.asl A src/mainboard/clevo/cml-u/board_info.txt A src/mainboard/clevo/cml-u/dsdt.asl A src/mainboard/clevo/cml-u/fmds/vboot-ro.fmd A src/mainboard/clevo/cml-u/fmds/vboot-roa.fmd A src/mainboard/clevo/cml-u/fmds/vboot-roab.fmd A src/mainboard/clevo/cml-u/ramstage.c A src/mainboard/clevo/cml-u/romstage.c A src/mainboard/clevo/cml-u/variants/n141cu/board_info.txt A src/mainboard/clevo/cml-u/variants/n141cu/data.vbt A src/mainboard/clevo/cml-u/variants/n141cu/devicetree.cb A src/mainboard/clevo/cml-u/variants/n141cu/gma-mainboard.ads A src/mainboard/clevo/cml-u/variants/n141cu/hda_verb.c A src/mainboard/clevo/cml-u/variants/n141cu/include/gpio_table.h 31 files changed, 1,681 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40581/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 32 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/n141cu: Add new Comet Lake mainboard
by Michael Niewöhner (Code Review) 07 May '20

07 May '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40581 ) Change subject: mb/clevo/n141cu: Add new Comet Lake mainboard ...................................................................... Patch Set 31: (1 comment) https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/ramstage.c: https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… PS31, Line 11: Make M.2 port configurable (SATA <> > It usually boils down to configuring a GPIO properly yeah, the flex io switch port (SATAXPCIE*) has to be NF1 -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 31 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner Gerrit-Comment-Date: Thu, 07 May 2020 12:45:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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coreboot-gerrit May 2020