coreboot-gerrit May 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: util/sconfig: Add LPC and ESPI buses
by Raul Rangel (Code Review) 07 May '20

07 May '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41099 ) Change subject: util/sconfig: Add LPC and ESPI buses ...................................................................... Uploaded patch set 3. -- To view, visit https://review.coreboot.org/c/coreboot/+/41099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 Gerrit-Change-Number: 41099 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 May 2020 18:56:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Add LPC and ESPI buses
by Raul Rangel (Code Review) 07 May '20

07 May '20

Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41099 to look at the new patch set (#3). Change subject: util/sconfig: Add LPC and ESPI buses ...................................................................... util/sconfig: Add LPC and ESPI buses Picasso has an LPC and eSPI bridge on the same PCI DEVFN. They can both be active at the same time. This adds a way to specify which devices belong on which bus. i.e., device pci 14.3 on # - D14F3 bridge device espi 0 on chip ec/google/chromeec device pnp 0c09.0 on end end end device lpc 0 on end end BUG=b:154445472 TEST=Built trembyle and saw static.c contained the espi bus. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 --- M src/device/device_const.c M src/device/device_util.c M src/include/device/path.h M util/sconfig/lex.yy.c_shipped M util/sconfig/main.c M util/sconfig/sconfig.l M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.tab.h_shipped M util/sconfig/sconfig.y 9 files changed, 200 insertions(+), 147 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/41099/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/41099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 Gerrit-Change-Number: 41099 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX
by Maxim Polyakov (Code Review) 07 May '20

07 May '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41116 ) Change subject: soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX ...................................................................... Patch Set 4: Code-Review+2 Need to resolve merge conflict -- To view, visit https://review.coreboot.org/c/coreboot/+/41116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cd25edd167ec71ee98c7ffa4fa6f95ca73a75e9 Gerrit-Change-Number: 41116 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 May 2020 18:51:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/n141cu: Add new Comet Lake mainboard
by Felix Singer (Code Review) 07 May '20

07 May '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40581 ) Change subject: mb/clevo/n141cu: Add new Comet Lake mainboard ...................................................................... Patch Set 34: (4 comments) https://review.coreboot.org/c/coreboot/+/40581/30/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/Kconfig: https://review.coreboot.org/c/coreboot/+/40581/30/src/mainboard/clevo/cml-u… PS30, Line 15: MAINBOARD_HAS_LPC_TPM > u sure? according to datasheet it's spi Done https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/Kconfig: https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… PS31, Line 18: select ONBOARD_VGA_IS_PRIMARY > As far as I understand the code, this configures the iGPU as the default graphics controller. Done https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/romstage.c: https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… PS31, Line 22: 0 > Any reason to disable ECT? Done https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/variants/n141cu/include/gpio_table.h: https://review.coreboot.org/c/coreboot/+/40581/31/src/mainboard/clevo/cml-u… PS31, Line 91: 0x04000201 > this will trigger an error "gpio_pad_reset_config_override: Logical to Chipset mapping not found" du […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 34 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner Gerrit-Comment-Date: Thu, 07 May 2020 18:20:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/n141cu: Add new Comet Lake mainboard
by Felix Singer (Code Review) 07 May '20

07 May '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40581 to look at the new patch set (#34). Change subject: mb/clevo/n141cu: Add new Comet Lake mainboard ...................................................................... mb/clevo/n141cu: Add new Comet Lake mainboard Add a new mainboard with the following specs: - Intel i5-10210U (Comet Lake) - Intel UHD graphics - Intel HD audio - 1x Ethernet 1Gbit/s - 1x SATA3 - 1x M.2 slot x4 (PCIe/SATA) - 1x M.2 slot x1 (WLAN/BT) - 1x 3G/LTE - USB2/3 - Thunderbolt - HDMI, mDP - CCD camera + mic - SD card reader - TPM2 SLB9670 The ACPI code has been taken from System76 CML-U mainboard series. Tested: - Clevo N141CU / TUXEDO InfinityBook Pro 14 v5 - SeaBIOS and TianoCore - vboot with RO, RO+A, RO+A+B - Booted Arch Linux - Linux 5.6.10 - Linux LTS 5.4.38 What works / What works not: - WLAN/BT does not work, but also not with vendor firmware. - Everything else works. Todos: - Missing libgfxinit support, since it does not support the Comet Lake platform yet. - Different configuration switches mentioned in ramstage.c. Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 --- M MAINTAINERS A src/mainboard/clevo/Kconfig A src/mainboard/clevo/Kconfig.name A src/mainboard/clevo/cml-u/Kconfig A src/mainboard/clevo/cml-u/Kconfig.name A src/mainboard/clevo/cml-u/Makefile.inc A src/mainboard/clevo/cml-u/acpi/ac.asl A src/mainboard/clevo/cml-u/acpi/battery.asl A src/mainboard/clevo/cml-u/acpi/buttons.asl A src/mainboard/clevo/cml-u/acpi/ec.asl A src/mainboard/clevo/cml-u/acpi/ec_ram.asl A src/mainboard/clevo/cml-u/acpi/gpe.asl A src/mainboard/clevo/cml-u/acpi/hid.asl A src/mainboard/clevo/cml-u/acpi/keyboard.asl A src/mainboard/clevo/cml-u/acpi/lid.asl A src/mainboard/clevo/cml-u/acpi/mainboard.asl A src/mainboard/clevo/cml-u/acpi/sleep.asl A src/mainboard/clevo/cml-u/acpi/tbt.asl A src/mainboard/clevo/cml-u/board_info.txt A src/mainboard/clevo/cml-u/dsdt.asl A src/mainboard/clevo/cml-u/fmds/vboot-ro.fmd A src/mainboard/clevo/cml-u/fmds/vboot-roa.fmd A src/mainboard/clevo/cml-u/fmds/vboot-roab.fmd A src/mainboard/clevo/cml-u/ramstage.c A src/mainboard/clevo/cml-u/romstage.c A src/mainboard/clevo/cml-u/variants/n141cu/board_info.txt A src/mainboard/clevo/cml-u/variants/n141cu/data.vbt A src/mainboard/clevo/cml-u/variants/n141cu/devicetree.cb A src/mainboard/clevo/cml-u/variants/n141cu/gma-mainboard.ads A src/mainboard/clevo/cml-u/variants/n141cu/hda_verb.c A src/mainboard/clevo/cml-u/variants/n141cu/include/gpio_table.h 31 files changed, 1,681 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40581/34 -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 34 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/sconfig: Add LPC and ESPI buses
by Furquan Shaikh (Code Review) 07 May '20

07 May '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41099 ) Change subject: util/sconfig: Add LPC and ESPI buses ...................................................................... Patch Set 2: You need to update device_util.c (dev_path) and device_const.c (path_eq) as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/41099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 Gerrit-Change-Number: 41099 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 May 2020 17:59:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/n141cu: Add new Comet Lake mainboard
by Felix Singer (Code Review) 07 May '20

07 May '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40581 to look at the new patch set (#33). Change subject: mb/clevo/n141cu: Add new Comet Lake mainboard ...................................................................... mb/clevo/n141cu: Add new Comet Lake mainboard Add a new mainboard with the following specs: - Intel i5-10210U (Comet Lake) - Intel UHD graphics - Intel HD audio - 1x Ethernet 1Gbit/s - 1x SATA3 - 1x M.2 slot x4 (PCIe/SATA) - 1x M.2 slot x1 (WLAN/BT) - 1x 3G/LTE - USB2/3 - Thunderbolt - HDMI, mDP - CCD camera + mic - SD card reader - TPM2 SLB9670 The ACPI code has been taken from System76 CML-U mainboard series. Tested: - Clevo N141CU / TUXEDO InfinityBook Pro 14 v5 - SeaBIOS and TianoCore - vboot with RO, RO+A, RO+A+B - Booted Arch Linux - Linux 5.6.10 - Linux LTS 5.4.38 What works / What works not: - WLAN/BT does not work, but also not with vendor firmware. - Everything else works. Todos: - Missing libgfxinit support, since it does not support the Comet Lake platform yet. - Different configuration switches mentioned in ramstage.c. Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 --- M MAINTAINERS A src/mainboard/clevo/Kconfig A src/mainboard/clevo/Kconfig.name A src/mainboard/clevo/cml-u/Kconfig A src/mainboard/clevo/cml-u/Kconfig.name A src/mainboard/clevo/cml-u/Makefile.inc A src/mainboard/clevo/cml-u/acpi/ac.asl A src/mainboard/clevo/cml-u/acpi/battery.asl A src/mainboard/clevo/cml-u/acpi/buttons.asl A src/mainboard/clevo/cml-u/acpi/ec.asl A src/mainboard/clevo/cml-u/acpi/ec_ram.asl A src/mainboard/clevo/cml-u/acpi/gpe.asl A src/mainboard/clevo/cml-u/acpi/hid.asl A src/mainboard/clevo/cml-u/acpi/keyboard.asl A src/mainboard/clevo/cml-u/acpi/lid.asl A src/mainboard/clevo/cml-u/acpi/mainboard.asl A src/mainboard/clevo/cml-u/acpi/sleep.asl A src/mainboard/clevo/cml-u/acpi/tbt.asl A src/mainboard/clevo/cml-u/board_info.txt A src/mainboard/clevo/cml-u/dsdt.asl A src/mainboard/clevo/cml-u/fmds/vboot-ro.fmd A src/mainboard/clevo/cml-u/fmds/vboot-roa.fmd A src/mainboard/clevo/cml-u/fmds/vboot-roab.fmd A src/mainboard/clevo/cml-u/ramstage.c A src/mainboard/clevo/cml-u/romstage.c A src/mainboard/clevo/cml-u/variants/n141cu/board_info.txt A src/mainboard/clevo/cml-u/variants/n141cu/data.vbt A src/mainboard/clevo/cml-u/variants/n141cu/devicetree.cb A src/mainboard/clevo/cml-u/variants/n141cu/gma-mainboard.ads A src/mainboard/clevo/cml-u/variants/n141cu/hda_verb.c A src/mainboard/clevo/cml-u/variants/n141cu/include/gpio_table.h 31 files changed, 1,684 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40581/33 -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 33 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Add Sata related UPDs configuration
by Sridhar Siricilla (Code Review) 07 May '20

07 May '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41029 ) Change subject: soc/intel/jasperlake: Add Sata related UPDs configuration ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/c/coreboot/+/41029/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41029/8//COMMIT_MSG@7 PS8, Line 7: Sata nit: SATA? https://review.coreboot.org/c/coreboot/+/41029/8//COMMIT_MSG@9 PS8, Line 9: This patch will allow to control Sata related UPDs from devicetree so : that UPD values can be configure as per each board's requirement. nit: This patch control SATA related UPDs based on the device tree cofiguration. -- To view, visit https://review.coreboot.org/c/coreboot/+/41029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f Gerrit-Change-Number: 41029 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 07 May 2020 16:45:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX
by Jonathan Zhang (Code Review) 07 May '20

07 May '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41116 ) Change subject: soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX ...................................................................... Patch Set 4: Code-Review+1 Thanks for doing this! LGTM. -- To view, visit https://review.coreboot.org/c/coreboot/+/41116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cd25edd167ec71ee98c7ffa4fa6f95ca73a75e9 Gerrit-Change-Number: 41116 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 May 2020 16:39:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: add generic SPDs
by Duncan Laurie (Code Review) 07 May '20

07 May '20

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40463 ) Change subject: mb/google/volteer: add generic SPDs ...................................................................... Patch Set 20: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4cd148e28efe458f2b312a7f1c5b6d71e8ef433 Gerrit-Change-Number: 40463 Gerrit-PatchSet: 20 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 May 2020 16:38:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2020