Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41099
to look at the new patch set (#3).
Change subject: util/sconfig: Add LPC and ESPI buses ......................................................................
util/sconfig: Add LPC and ESPI buses
Picasso has an LPC and eSPI bridge on the same PCI DEVFN. They can both be active at the same time. This adds a way to specify which devices belong on which bus.
i.e., device pci 14.3 on # - D14F3 bridge device espi 0 on chip ec/google/chromeec device pnp 0c09.0 on end end end device lpc 0 on end end
BUG=b:154445472 TEST=Built trembyle and saw static.c contained the espi bus.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 --- M src/device/device_const.c M src/device/device_util.c M src/include/device/path.h M util/sconfig/lex.yy.c_shipped M util/sconfig/main.c M util/sconfig/sconfig.l M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.tab.h_shipped M util/sconfig/sconfig.y 9 files changed, 200 insertions(+), 147 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/41099/3