coreboot-gerrit May 2020

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Change in coreboot[master]: sb/intel/common: Improve code formatting
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40258 ) Change subject: sb/intel/common: Improve code formatting ...................................................................... sb/intel/common: Improve code formatting Change-Id: I62a213013d9008d8a4a22b5908b7fc7d1b663c4b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/common/finalize.c M src/southbridge/intel/common/madt.c M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/common/rtc.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/common/smihandler.c 6 files changed, 16 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/40258/1 diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 4c6cc63..e956965 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -15,8 +15,7 @@ { const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - if (CONFIG(LOCK_SPI_FLASH_RO) || - CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) { + if (CONFIG(LOCK_SPI_FLASH_RO) || CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) { int i; u32 lockmask = 1UL << 31; if (CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) @@ -43,8 +42,7 @@ pci_or_config16(lpc_dev, D31F0_GEN_PMCON_1, SMI_LOCK); - pci_or_config8(lpc_dev, D31F0_GEN_PMCON_LOCK, - ACPI_BASE_LOCK | SLP_STR_POL_LOCK); + pci_or_config8(lpc_dev, D31F0_GEN_PMCON_LOCK, ACPI_BASE_LOCK | SLP_STR_POL_LOCK); pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK); @@ -54,8 +52,7 @@ /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); - pci_write_config32(PCI_DEV(0, 27, 0), 0x74, - pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); + pci_write_config32(PCI_DEV(0, 27, 0), 0x74, pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK); diff --git a/src/southbridge/intel/common/madt.c b/src/southbridge/intel/common/madt.c index 3385270..d425a74 100644 --- a/src/southbridge/intel/common/madt.c +++ b/src/southbridge/intel/common/madt.c @@ -11,8 +11,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 620d9fa..e1da606 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -16,8 +16,7 @@ D26IR, D27IR, D28IR, D29IR, D30IR, D31IR, }; -enum pirq intel_common_map_pirq(const struct device *dev, - const enum pci_pin pci_pin) +enum pirq intel_common_map_pirq(const struct device *dev, const enum pci_pin pci_pin) { u8 slot = PCI_SLOT(dev->path.pci.devfn); u8 shift = 4 * (pci_pin - PCI_INT_A); @@ -25,8 +24,7 @@ u16 reg; if (pci_pin < PCI_INT_A || pci_pin > PCI_INT_D) { - printk(BIOS_ERR, - "ACPI_PIRQ_GEN: Slot %d PCI pin %d out of bounds\n", + printk(BIOS_ERR, "ACPI_PIRQ_GEN: Slot %d PCI pin %d out of bounds\n", slot, pci_pin); return PIRQ_NONE; } diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c index f4ac9f0..26ca65c 100644 --- a/src/southbridge/intel/common/rtc.c +++ b/src/southbridge/intel/common/rtc.c @@ -19,8 +19,7 @@ int rtc_failure(void) { - return !!(pci_read_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3) - & RTC_BATTERY_DEAD); + return !!(pci_read_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3) & RTC_BATTERY_DEAD); } void sb_rtc_init(void) @@ -30,8 +29,7 @@ if (rtc_failed) { if (CONFIG(ELOG)) elog_add_event(ELOG_TYPE_RTC_RESET); - pci_update_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3, - ~RTC_BATTERY_DEAD, 0); + pci_update_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0); } printk(BIOS_DEBUG, "RTC: failed = 0x%x\n", rtc_failed); diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 17ac5110..222c4a4 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -110,8 +110,7 @@ return 0; /* These status bits do not imply completion of transaction. */ - status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | - SMBHSTSTS_SMBALERT_STS); + status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | SMBHSTSTS_SMBALERT_STS); return status != 0; } @@ -127,8 +126,7 @@ static int cb_err_from_stat(u8 status) { /* These status bits do not imply errors. */ - status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | - SMBHSTSTS_SMBALERT_STS); + status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | SMBHSTSTS_SMBALERT_STS); if (status == SMBHSTSTS_INTR) return 0; @@ -182,8 +180,7 @@ } while (--loops && status == 0); if (loops == 0) - return recover_master(base, - SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT); + return recover_master(base, SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT); return 0; } @@ -199,8 +196,7 @@ } while (--loops && !host_completed(status)); if (loops == 0) - return recover_master(base, - SMBUS_WAIT_UNTIL_DONE_TIMEOUT); + return recover_master(base, SMBUS_WAIT_UNTIL_DONE_TIMEOUT); return cb_err_from_stat(status); } @@ -317,8 +313,7 @@ /* Indicate that next byte is the last one. */ if (sw_drives_nak && (bytes + 1 >= max_bytes)) { - host_and_or(base, SMBHSTCTL, 0xff, - SMBHSTCNT_LAST_BYTE); + host_and_or(base, SMBHSTCTL, 0xff, SMBHSTCNT_LAST_BYTE); } } @@ -421,8 +416,7 @@ /* Only since ICH5 */ static int has_i2c_read_command(void) { - if (CONFIG(SOUTHBRIDGE_INTEL_I82371EB) || - CONFIG(SOUTHBRIDGE_INTEL_I82801DX)) + if (CONFIG(SOUTHBRIDGE_INTEL_I82371EB) || CONFIG(SOUTHBRIDGE_INTEL_I82801DX)) return 0; return 1; } @@ -440,8 +434,7 @@ * some revision of PCH. Presumably hardware revisions that * do not have i2c block write support internally set LSB. */ - ret = setup_command(base, I801_I2C_BLOCK_DATA, - XMIT_WRITE(device)); + ret = setup_command(base, I801_I2C_BLOCK_DATA, XMIT_WRITE(device)); if (ret < 0) return ret; diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7d4066d..9133a53 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -78,8 +78,7 @@ /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { + if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) { unsigned int buses; buses = pci_read_config32(dev, PCI_PRIMARY_BUS); busmaster_disable_on_bus((buses >> 8) & 0xff); -- To view, visit https://review.coreboot.org/c/coreboot/+/40258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62a213013d9008d8a4a22b5908b7fc7d1b663c4b Gerrit-Change-Number: 40258 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: lp/drivers/usb: Add quirk for QEMU XHCI root hub
by Duncan Laurie (Code Review) 01 May '20

01 May '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39839 ) Change subject: lp/drivers/usb: Add quirk for QEMU XHCI root hub ...................................................................... lp/drivers/usb: Add quirk for QEMU XHCI root hub The QEMU XHCI driver does not implement the Port Change Detect bit in the USBSTS register. As a result no devices are attached without looking at each port individually. Detect this as a quirk based on the QEMU XHCI controller PCI ID, and apply it to the root hub quirk list so it can get used by the generic hub driver to skip this check. With this change an attached USB mass storage device is detected and able to boot when supplied to qemu: -drive if=none,id=usbmsc,format=raw,file=/tmp/disk.img -device qemu-xhci,id-xhci -device usb-storage,bus=xhci.0,drive=usbmsc Change-Id: I6689cb1dbb24c93d45f5c5ef040b713925d07588 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M payloads/libpayload/drivers/usb/generic_hub.c M payloads/libpayload/drivers/usb/quirks.c M payloads/libpayload/drivers/usb/xhci.c M payloads/libpayload/include/usb/usb.h 4 files changed, 35 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/39839/1 diff --git a/payloads/libpayload/drivers/usb/generic_hub.c b/payloads/libpayload/drivers/usb/generic_hub.c index 9d444ee..7263400 100644 --- a/payloads/libpayload/drivers/usb/generic_hub.c +++ b/payloads/libpayload/drivers/usb/generic_hub.c @@ -218,9 +218,11 @@ if (!hub) return; - if (hub->ops->hub_status_changed && - hub->ops->hub_status_changed(dev) != 1) + if (!(dev->quirks & USB_QUIRK_HUB_NO_USBSTS_PCD) && + hub->ops->hub_status_changed && + hub->ops->hub_status_changed(dev) != 1) { return; + } int port; for (port = 1; port <= hub->num_ports; ++port) { diff --git a/payloads/libpayload/drivers/usb/quirks.c b/payloads/libpayload/drivers/usb/quirks.c index 0a35149..556ce9e 100644 --- a/payloads/libpayload/drivers/usb/quirks.c +++ b/payloads/libpayload/drivers/usb/quirks.c @@ -59,6 +59,31 @@ */ }; +#if CONFIG(LP_USB_PCI) +usb_quirks_t pci_quirks[] = { + /* QEMU XHCI root hub does not implement port change detect */ + { 0x1b36, 0x000d, USB_QUIRK_HUB_NO_USBSTS_PCD, 0 }, +}; + +u32 pci_quirk_check(pcidev_t controller) +{ + int i; + u16 vendor = pci_read_config16(controller, REG_VENDOR_ID); + u16 device = pci_read_config16(controller, REG_DEVICE_ID); + + for (i = 0; i < ARRAY_SIZE(pci_quirks); i++) { + if ((pci_quirks[i].vendor == vendor) && + (pci_quirks[i].device == device)) { + printf("PCI quirks enabled: %08x\n", + pci_quirks[i].quirks); + return pci_quirks[i].quirks; + } + } + + return USB_QUIRK_NONE; +} +#endif + u32 usb_quirk_check(u16 vendor, u16 device) { int i; diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 659861f..55ca89f 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -316,9 +316,13 @@ controller = xhci_init((unsigned long)reg_addr); if (controller) { + xhci_t *xhci = controller->instance; controller->pcidev = addr; xhci_switch_ppt_ports(addr); + + /* Set up any quirks for controller root hub */ + xhci->roothub->quirks = pci_quirk_check(addr); } return controller; diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index 5d27f7c..328e883 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -318,6 +318,7 @@ int usb_attach_device(hci_t *controller, int hubaddress, int port, usb_speed speed); +u32 pci_quirk_check(pcidev_t controller); u32 usb_quirk_check(u16 vendor, u16 device); int usb_interface_check(u16 vendor, u16 device); @@ -330,6 +331,7 @@ #define USB_QUIRK_MSC_FORCE_TRANS_CBI_I (1 << 6) #define USB_QUIRK_MSC_NO_TEST_UNIT_READY (1 << 7) #define USB_QUIRK_MSC_SHORT_INQUIRY (1 << 8) +#define USB_QUIRK_HUB_NO_USBSTS_PCD (1 << 9) #define USB_QUIRK_TEST (1 << 31) #define USB_QUIRK_NONE 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/39839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6689cb1dbb24c93d45f5c5ef040b713925d07588 Gerrit-Change-Number: 39839 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

6 11

Change in coreboot[master]: mb/google/wheelie: add new variant for wheelie
by Peichao Li (Code Review) 01 May '20

01 May '20

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40587 ) Change subject: mb/google/wheelie: add new variant for wheelie ...................................................................... mb/google/wheelie: add new variant for wheelie Add initial support for wheelie variant board. BUG=b:154664137 BRANCH=None TEST=build Signed-off-by: peichao.wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: Id638e987f45c247dae824f221a38ccf32626572f --- A src/mainboard/google/dedede/variants/wheelie/Makefile.inc A src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h A src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h A src/mainboard/google/dedede/variants/wheelie/overridetree.cb 4 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/40587/1 diff --git a/src/mainboard/google/dedede/variants/wheelie/Makefile.inc b/src/mainboard/google/dedede/variants/wheelie/Makefile.inc new file mode 100644 index 0000000..13afb36 --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/Makefile.inc @@ -0,0 +1,8 @@ +## +## This file is part of the coreboot project. +## +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +SPD_SOURCES = Micron_MT53E512M32D2NP_2GB #0b0000 diff --git a/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h b/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h new file mode 100644 index 0000000..70bd8e7 --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h @@ -0,0 +1,13 @@ +/* + * This file is part of the coreboot project. + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h b/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h new file mode 100644 index 0000000..fd92743 --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* + * This file is part of the coreboot project. + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/wheelie/overridetree.cb b/src/mainboard/google/dedede/variants/wheelie/overridetree.cb new file mode 100644 index 0000000..75ef7f7 --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/overridetree.cb @@ -0,0 +1 @@ +chip soc/intel/jasperlake -- To view, visit https://review.coreboot.org/c/coreboot/+/40587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id638e987f45c247dae824f221a38ccf32626572f Gerrit-Change-Number: 40587 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 23

Change in coreboot[master]: mb/google/nightfury: Tune the usb2_port[0] strength
by shkim (Code Review) 01 May '20

01 May '20

Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40622 to review the following change. Change subject: mb/google/nightfury: Tune the usb2_port[0] strength ...................................................................... mb/google/nightfury: Tune the usb2_port[0] strength Update usb2 port strength parameter for usb2_port[0] to improve SI. BUG=b:154668734 BRANCH=firmware-hatch-12672.B TEST=Built and checked SI margin of USB2 ports Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f --- M src/mainboard/google/hatch/variants/nightfury/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/40622/1 diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 4b985d9..2c759bc 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -23,7 +23,7 @@ # Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY" -- To view, visit https://review.coreboot.org/c/coreboot/+/40622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f Gerrit-Change-Number: 40622 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/intel/jasperlake: Add support to generate ACPI GPIO operations
by Karthik Ramasubramanian (Code Review) 01 May '20

01 May '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40536 ) Change subject: soc/intel/jasperlake: Add support to generate ACPI GPIO operations ...................................................................... soc/intel/jasperlake: Add support to generate ACPI GPIO operations Add support to generate ACPI operations to get/set/clear RX/TX GPIOs. BUG=b:152936541 TEST=Build and boot the mainboard. Ensure that there are no errors in the coreboot logs regarding unsupported ACPI GPIO operations. Change-Id: Ibc4846fbd9baf4f22c48c82acefed960669ed7d4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/jasperlake/acpi.c 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40536/1 diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 29a4619..d8b695b 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -330,3 +330,40 @@ { return MP_IRQ_POLARITY_HIGH; } + +static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) +{ + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); + return 0; +} + +static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) +{ + /* Store (op (gpio_num), Local0) */ + acpigen_write_store(); + acpigen_soc_gpio_op(op, gpio_num); + acpigen_emit_byte(LOCAL0_OP); + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc4846fbd9baf4f22c48c82acefed960669ed7d4 Gerrit-Change-Number: 40536 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
by Patrick Georgi (Code Review) 01 May '20

01 May '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39895 ) Change subject: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time ...................................................................... mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time Update UPD IIO bifurcation at run-time according to different Riser cards. For detail please reference Facebook Server Intel Motherboard v4.0, Sec. 10.1.2 Riser card types. With the engineering build FSP, it can only configure IIO for one socket so my local test needs to remove all socket1 elements from tp_iio_bifur_table. This change relies on [1] and need to add GPP_C15 and GPP_C16 to early_gpio_table for gpio configuration in bootblock. [1] https://review.coreboot.org/c/coreboot/+/39427/ Tested=OCP Tioga Pass can see socket0 IIO being updated with an engineering build FSP. Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39895 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/romstage.c M src/mainboard/ocp/tiogapass/skxsp_tp_iio.h 2 files changed, 35 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, approved diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 8f9806f..e4a188d 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -16,10 +16,29 @@ #include <fsp/api.h> #include <FspmUpd.h> #include <soc/romstage.h> +#include <string.h> +#include <gpio.h> +#include <soc/lewisburg_pch_gpio_defs.h> #include "skxsp_tp_gpio.h" #include "skxsp_tp_iio.h" +static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)]; + +static void oem_update_iio(FSPM_UPD *mupd) +{ + /* Read GPIO to decide IIO bifurcation at run-time. */ + int slot_config0 = gpio_get(GPP_C15); + int slot_config1 = gpio_get(GPP_C16); + + /* It's a single side 3 slots riser card, to tell which AICs are on each slot requires + reading the GPIO expander PCA9555 via SMBUS, and then configure the bifurcation + accordingly is left for future work. */ + if (!slot_config0 && slot_config1) + mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable[Skt0_Iou0].Bifurcation + = IIO_BIFURCATE_xxx8xxx8; +} + /* * Configure GPIO depend on platform */ @@ -32,8 +51,9 @@ static void mainboard_config_iio(FSPM_UPD *mupd) { + memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table)); mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable = - (UPD_IIO_BIFURCATION_DATA_ENTRY *) tp_iio_bifur_table; + (UPD_IIO_BIFURCATION_DATA_ENTRY *) iio_table_buf; mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries = ARRAY_SIZE(tp_iio_bifur_table); @@ -49,6 +69,7 @@ mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00; mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00; + oem_update_iio(mupd); } void mainboard_memory_init_params(FSPM_UPD *mupd) diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h index 4037020..d436e88 100644 --- a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h +++ b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h @@ -19,6 +19,19 @@ #include <FspmUpd.h> #include <soc/pci_devs.h> +enum tp_iio_bifur_table_index { + Skt0_Iou0 = 0, + Skt0_Iou1, + Skt0_Iou2, + Skt0_Mcp0, + Skt0_Mcp1, + Skt1_Iou0, + Skt1_Iou1, + Skt1_Iou2, + Skt1_Mcp0, + Skt1_Mcp1 +}; + /* * Standard Tioga Pass Iio Bifurcation Table * This is SS 2x16 config. As documented in OCP TP spec, there are -- To view, visit https://review.coreboot.org/c/coreboot/+/39895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Gerrit-Change-Number: 39895 Gerrit-PatchSet: 11 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: vendorcode/intel/fsp: update Cooperlake-SP header files
by Jonathan Zhang (Code Review) 01 May '20

01 May '20

Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Andrey Petrov, David Hendricks, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40034 to look at the new patch set (#6). Change subject: vendorcode/intel/fsp: update Cooperlake-SP header files ...................................................................... vendorcode/intel/fsp: update Cooperlake-SP header files Update Cooperlake-SP (CPX-SP) FSP header files. As CPX-SP FSP engineering is on-going (the processor Mass Production is some time in this year). These header files will be adjusted when changes are necessary with newer FSP release. This commit corresponds to FSP release 1025293. Also update soc/xeon_sp code file and Skylake-SP header file accordingly to use FsptPort80RouteDisable instead of PcdPort80RouteDisable. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: I8bc6882e47de23d83ba0f521bb12a10dace523ce --- M src/soc/intel/xeon_sp/bootblock.c M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h M src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/FspUpd.h M src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/FsptUpd.h A src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/gpio_fsp.h A src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/hob_iiouds.h A src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/hob_memmap.h 9 files changed, 1,384 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40034/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/40034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bc6882e47de23d83ba0f521bb12a10dace523ce Gerrit-Change-Number: 40034 Gerrit-PatchSet: 6 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/tiogapass: exclude the consequences of reconfig GPIO in FSP-M
by Maxim Polyakov (Code Review) 01 May '20

01 May '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40730 ) Change subject: mb/tiogapass: exclude the consequences of reconfig GPIO in FSP-M ...................................................................... mb/tiogapass: exclude the consequences of reconfig GPIO in FSP-M FSP-M can reconfigure the GPIO controller inside Lewisburg PCH. Since FSP-M is provided as a binary file, we will not be able to change the contents inside of this file. We should be sure that after romstage the pads will be configured according to the configuration from gpio.h only. This patch reconfigures the GPIO to ramstage. Change-Id: I2959711db45eaa034c9c2dec1d64b0394efdbb71 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/ramstage.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/40730/1 diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 16b4fd9..fba1d80 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -14,11 +14,12 @@ */ #include <soc/ramstage.h> #include <bootstate.h> -#include <gpio.h> -#include <soc/lewisburg_pch_gpio_defs.h> +#include "gpio.h" void mainboard_silicon_init_params(FSPS_UPD *params) { + /* configure Lewisburg PCH GPIO controller after FSP-M */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } static void pull_post_complete_pin(void *unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/40730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2959711db45eaa034c9c2dec1d64b0394efdbb71 Gerrit-Change-Number: 40730 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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