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Change in coreboot[master]: mb/purism/librem_skl: Use ACPI backlight controls
by Patrick Georgi (Code Review) 01 May '20

01 May '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40145 ) Change subject: mb/purism/librem_skl: Use ACPI backlight controls ...................................................................... mb/purism/librem_skl: Use ACPI backlight controls Enables ACPI backlight controls. Change-Id: Iccf50f427b7555ee1a3ef9cc11a89d532789ac54 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40145 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn(a)eltan.com> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem_skl/dsdt.asl M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb 3 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Wim Vervoorn: Looks good to me, but someone else must approve Frans Hendriks: Looks good to me, but someone else must approve diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index 687de93..5ef19e1 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -24,6 +24,7 @@ { #include <soc/intel/skylake/acpi/systemagent.asl> #include <soc/intel/skylake/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index f69c482..6c55af6 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -8,6 +8,9 @@ register "gpu_pch_backlight_pwm_hz" = "200" + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" register "deep_s5_enable_ac" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index f5b8b99..f481352 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -8,6 +8,9 @@ register "gpu_pch_backlight_pwm_hz" = "200" + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" register "deep_s5_enable_ac" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/40145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf50f427b7555ee1a3ef9cc11a89d532789ac54 Gerrit-Change-Number: 40145 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: security/vboot: Convert reboot-related errors to vboot2-style
by Yu-Ping Wu (Code Review) 01 May '20

01 May '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40749 ) Change subject: security/vboot: Convert reboot-related errors to vboot2-style ...................................................................... security/vboot: Convert reboot-related errors to vboot2-style Error codes are renamed as follows: VBERROR_SHUTDOWN_REQUESTED --> VB2_REQUEST_SHUTDOWN VBERROR_REBOOT_REQUIRED --> VB2_REQUEST_REBOOT VBERROR_EC_REBOOT_TO_SWITCH_RW --> VB2_REQUEST_REBOOT_EC_SWITCH_RW VBERROR_EC_REBOOT_TO_RO_REQUIRED --> VB2_REQUEST_REBOOT_EC_TO_RO BRANCH=none BUG=b:124141368, chromium:988410 TEST=emerge-nami coreboot Change-Id: Id82cf85f49dfb63a9c3d41aacd3969786bffcac7 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/security/vboot/ec_sync.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/40749/1 diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index 580e6c6..39950a8 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -56,7 +56,7 @@ case VB2_SUCCESS: break; - case VBERROR_EC_REBOOT_TO_RO_REQUIRED: + case VB2_REQUEST_REBOOT_EC_TO_RO: printk(BIOS_INFO, "EC Reboot requested. Doing cold reboot\n"); if (google_chromeec_reboot(0, EC_REBOOT_COLD, 0)) printk(BIOS_EMERG, "Failed to get EC to cold reboot\n"); @@ -65,7 +65,7 @@ break; /* Only for EC-EFS */ - case VBERROR_EC_REBOOT_TO_SWITCH_RW: + case VB2_REQUEST_REBOOT_EC_SWITCH_RW: printk(BIOS_INFO, "Switch EC slot requested. Doing cold reboot\n"); if (google_chromeec_reboot(0, EC_REBOOT_COLD, EC_REBOOT_FLAG_SWITCH_RW_SLOT)) @@ -74,7 +74,7 @@ halt(); break; - case VBERROR_REBOOT_REQUIRED: + case VB2_REQUEST_REBOOT: printk(BIOS_INFO, "Reboot requested. Doing warm reboot\n"); vboot_reboot(); break; @@ -203,7 +203,7 @@ if (!enable) { /* If protection is still enabled, need reboot */ if (resp.flags & protected_region) - return VBERROR_EC_REBOOT_TO_RO_REQUIRED; + return VB2_REQUEST_REBOOT_EC_TO_RO; return VB2_SUCCESS; } @@ -222,7 +222,7 @@ /* If RW will be protected at boot but not now, need a reboot */ if (resp.flags & EC_FLASH_PROTECT_ALL_AT_BOOT) - return VBERROR_EC_REBOOT_TO_RO_REQUIRED; + return VB2_REQUEST_REBOOT_EC_TO_RO; /* Otherwise, it's an error */ return VB2_ERROR_UNKNOWN; @@ -479,7 +479,7 @@ if (limit_power) { printk(BIOS_INFO, "EC requests limited power usage. Request shutdown.\n"); - return VBERROR_SHUTDOWN_REQUESTED; + return VB2_REQUEST_SHUTDOWN; } else { printk(BIOS_INFO, "Waited %luus to clear limit power flag.\n", stopwatch_duration_usecs(&sw)); -- To view, visit https://review.coreboot.org/c/coreboot/+/40749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id82cf85f49dfb63a9c3d41aacd3969786bffcac7 Gerrit-Change-Number: 40749 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: Update vboot submodule to upstream master
by Yu-Ping Wu (Code Review) 01 May '20

01 May '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40845 ) Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 55154620: vboot: Add screens for recovery using disk to commit id 3aab3014: vboot: Convert reboot-related errors to vboot2-style This brings in 3 new commits. Change-Id: I75be535e0b0f8080366b98e5ae2007452ad51738 Signed-off-by: Yu-Ping Wu <yupingso(a)google.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/40845/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 5515462..3aab301 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 55154620f4aa3bba9eaaf09f5186a52a48720025 +Subproject commit 3aab301473ec0b95f109a245efeadc20c3b7d57d -- To view, visit https://review.coreboot.org/c/coreboot/+/40845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75be535e0b0f8080366b98e5ae2007452ad51738 Gerrit-Change-Number: 40845 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree
by Meera Ravindranath (Code Review) 01 May '20

01 May '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40832 ) Change subject: soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree ...................................................................... soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree This CL adds support to fill PcieRpClkReqDetect UPD from devicetree. Filling this UPD will allow FSP to enable proper clksrc gpio configuration. BUG=None BRANCH=None TEST=Build and boot tglrvp. Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/40832/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index a3319d4..fe33835 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -107,6 +107,9 @@ * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ + uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ enum L1_substates_control { L1_SS_FSP_DEFAULT, diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 5acad20..fc2a3c0 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -151,6 +151,11 @@ params->PcieRpAdvancedErrorReporting[i] = config->PcieRpAdvancedErrorReporting[i]; } + + /* Enable ClkReqDetect for enabled port */ + memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, + sizeof(config->PcieRpClkReqDetect)); + /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/40832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7 Gerrit-Change-Number: 40832 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/hatch/vr/puff: Add psys_pmax calculation
by Tim Chen (Code Review) 01 May '20

01 May '20

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40828 to review the following change. Change subject: mb/google/hatch/vr/puff: Add psys_pmax calculation ...................................................................... mb/google/hatch/vr/puff: Add psys_pmax calculation This patch adds psys_pmax calculation. There are two types of power sources. One is barrel jack and the other is USB TYPE-C. The voltage level is fixed for a barrel jack while TYPE-C may vary depending on power ratings. We need to get voltage information from EC and calculate correct psys_pmax value. The psys_pmax needs to be set before FSP-S since FSP-S will handle the setting passing to pcode, so move the routine ahead to variant_ramstage_init. BUG=b:151972149 TEST=emerge-puff coreboot chromeos-bootimage check firmware log and ensure psys_pmax is passed to FSP check the data from dump_intel_rapl_consumption in the OS and ensure the power data is close to an external power meter. Change-Id: Iff767d4b44a01e766258345545438a54a16d1af5 Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/duffy/mainboard.c M src/mainboard/google/hatch/variants/kaisa/mainboard.c 2 files changed, 74 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/40828/1 diff --git a/src/mainboard/google/hatch/variants/duffy/mainboard.c b/src/mainboard/google/hatch/variants/duffy/mainboard.c index 3f74c96..ceeb0c5 100644 --- a/src/mainboard/google/hatch/variants/duffy/mainboard.c +++ b/src/mainboard/google/hatch/variants/duffy/mainboard.c @@ -31,23 +31,6 @@ stopwatch_duration_msecs(&sw)); } -void variant_ramstage_init(void) -{ - static const long display_timeout_ms = 3000; - - /* This is reconfigured back to whatever FSP-S expects by - gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - gpio_input(GPIO_DP_HPD); - if (display_init_required() - && !gpio_get(GPIO_HDMI_HPD) - && !gpio_get(GPIO_DP_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } -} - /* * For type-C chargers, set PL2 to 90% of max power to account for * cable loss and FET Rdson loss in the path from the source. @@ -86,6 +69,24 @@ * | n (U22) | 29 | .9n | .9n | x(43) | * +-------------+-----+---------+---------+-------+ */ + +/* + * Psys_pmax considerations + * + * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A + * instead of real system power. The equation is shown below: + * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) + * Hence, Iinput (Amps) = 9.6A + * Since there is no voltage information from PSYS, different voltage input + * would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W + * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W + * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W + */ +#define PSYS_IMAX 9600 +#define BJ_VOLTS_MV 19000 + static void mainboard_set_power_limits(config_t *conf) { enum usb_chg_type type; @@ -108,15 +109,33 @@ /* set minimum duty cycle */ conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + } else { + /* Input type is barrel jack */ + volts_mv = BJ_VOLTS_MV; } + /* voltage unit is milliVolts and current is in milliAmps */ + conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); conf->tdp_pl2_override = PUFF_PL2; /* set psyspl2 to 90% of max adapter power */ conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); } -void variant_mainboard_enable(struct device *dev) +void variant_ramstage_init(void) { + static const long display_timeout_ms = 3000; config_t *conf = config_of_soc(); + + /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ + gpio_input(GPIO_HDMI_HPD); + gpio_input(GPIO_DP_HPD); + if (display_init_required() + && !gpio_get(GPIO_HDMI_HPD) + && !gpio_get(GPIO_DP_HPD)) { + /* This has to be done before FSP-S runs. */ + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } + /* Psys_pmax needs to be setup before FSP-S */ mainboard_set_power_limits(conf); } diff --git a/src/mainboard/google/hatch/variants/kaisa/mainboard.c b/src/mainboard/google/hatch/variants/kaisa/mainboard.c index 3f74c96..ceeb0c5 100644 --- a/src/mainboard/google/hatch/variants/kaisa/mainboard.c +++ b/src/mainboard/google/hatch/variants/kaisa/mainboard.c @@ -31,23 +31,6 @@ stopwatch_duration_msecs(&sw)); } -void variant_ramstage_init(void) -{ - static const long display_timeout_ms = 3000; - - /* This is reconfigured back to whatever FSP-S expects by - gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - gpio_input(GPIO_DP_HPD); - if (display_init_required() - && !gpio_get(GPIO_HDMI_HPD) - && !gpio_get(GPIO_DP_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } -} - /* * For type-C chargers, set PL2 to 90% of max power to account for * cable loss and FET Rdson loss in the path from the source. @@ -86,6 +69,24 @@ * | n (U22) | 29 | .9n | .9n | x(43) | * +-------------+-----+---------+---------+-------+ */ + +/* + * Psys_pmax considerations + * + * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A + * instead of real system power. The equation is shown below: + * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) + * Hence, Iinput (Amps) = 9.6A + * Since there is no voltage information from PSYS, different voltage input + * would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W + * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W + * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W + */ +#define PSYS_IMAX 9600 +#define BJ_VOLTS_MV 19000 + static void mainboard_set_power_limits(config_t *conf) { enum usb_chg_type type; @@ -108,15 +109,33 @@ /* set minimum duty cycle */ conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + } else { + /* Input type is barrel jack */ + volts_mv = BJ_VOLTS_MV; } + /* voltage unit is milliVolts and current is in milliAmps */ + conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); conf->tdp_pl2_override = PUFF_PL2; /* set psyspl2 to 90% of max adapter power */ conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); } -void variant_mainboard_enable(struct device *dev) +void variant_ramstage_init(void) { + static const long display_timeout_ms = 3000; config_t *conf = config_of_soc(); + + /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ + gpio_input(GPIO_HDMI_HPD); + gpio_input(GPIO_DP_HPD); + if (display_init_required() + && !gpio_get(GPIO_HDMI_HPD) + && !gpio_get(GPIO_DP_HPD)) { + /* This has to be done before FSP-S runs. */ + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } + /* Psys_pmax needs to be setup before FSP-S */ mainboard_set_power_limits(conf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff767d4b44a01e766258345545438a54a16d1af5 Gerrit-Change-Number: 40828 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: payloads: Fix 16-bit read/write to PCI_COMMAND registe
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40743 ) Change subject: payloads: Fix 16-bit read/write to PCI_COMMAND registe ...................................................................... payloads: Fix 16-bit read/write to PCI_COMMAND registe Change-Id: I34facbe0cbbdc91066799b586d96abca1599c509 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M payloads/libpayload/drivers/usb/ehci.c M payloads/libpayload/drivers/usb/usbinit.c 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/40743/1 diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index bf8a5ea..7969feb 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -860,9 +860,9 @@ hci_t *controller; u32 reg_base; - u32 pci_command = pci_read_config32(addr, PCI_COMMAND); + u16 pci_command = pci_read_config16(addr, PCI_COMMAND); pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO ; - pci_write_config32(addr, PCI_COMMAND, pci_command); + pci_write_config16(addr, PCI_COMMAND, pci_command); reg_base = pci_read_config32 (addr, USBBASE); diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index 0ac27e4..49634c6 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -62,11 +62,11 @@ /* enable busmaster */ if (devclass == 0xc03) { - u32 pci_command; + u16 pci_command; - pci_command = pci_read_config32(pci_device, PCI_COMMAND); + pci_command = pci_read_config16(pci_device, PCI_COMMAND); pci_command |= PCI_COMMAND_MASTER; - pci_write_config32(pci_device, PCI_COMMAND, pci_command); + pci_write_config16(pci_device, PCI_COMMAND, pci_command); usb_debug("%02x:%02x.%x %04x:%04x.%d ", bus, dev, func, pciid >> 16, pciid & 0xFFFF, func); -- To view, visit https://review.coreboot.org/c/coreboot/+/40743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34facbe0cbbdc91066799b586d96abca1599c509 Gerrit-Change-Number: 40743 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND register
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40742 ) Change subject: sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND register ...................................................................... sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND register Change-Id: Ib403f5a231f86bdc60b956e72a4ae631aa6a3899 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/common/smihandler.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40742/1 diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7d4066d..7b27ce0 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -61,7 +61,7 @@ for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -71,9 +71,9 @@ continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); -- To view, visit https://review.coreboot.org/c/coreboot/+/40742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib403f5a231f86bdc60b956e72a4ae631aa6a3899 Gerrit-Change-Number: 40742 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Enable USB port for camera support
by Ian Feng (Code Review) 01 May '20

01 May '20

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40774 ) Change subject: mb/google/dedede: Enable USB port for camera support ...................................................................... mb/google/dedede: Enable USB port for camera support Support USB Chicony user facing camera. BUG=b:155109736 BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using user facing camera. Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I7580a58086977e239dca49c1def4f03583831662 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/40774/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cfe221f..c7cf5db 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -32,7 +32,7 @@ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not Used register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Integrated Bluetooth @@ -212,6 +212,11 @@ device usb 2.4 on end end chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi register "desc" = ""Integrated Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" -- To view, visit https://review.coreboot.org/c/coreboot/+/40774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7580a58086977e239dca49c1def4f03583831662 Gerrit-Change-Number: 40774 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801jx: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40795 ) Change subject: sb/intel/i82801jx: Fix 16-bit read/write PCI_COMMAND register ...................................................................... sb/intel/i82801jx: Fix 16-bit read/write PCI_COMMAND register Change-Id: If39cdfb21fec307141593f2482e014e146d4f1f2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/i82801jx/usb_ehci.c 4 files changed, 4 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/40795/1 diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 1711de9..5da7ce5 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -247,8 +247,7 @@ pci_write_config32(dev, 0x120, reg32); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); reg8 = pci_read_config8(dev, 0x4d); // Docking Status reg8 &= ~(1 << 7); // Docking not supported diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index e55735b..f3c899c 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -13,12 +13,8 @@ static void i82801jx_enable_device(struct device *dev) { - u32 reg32; - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } static void i82801jx_early_settings(const config_t *const info) diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index dba1a65..df3140a 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -20,9 +20,7 @@ printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n"); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c index 03b314a..45737a5 100644 --- a/src/southbridge/intel/i82801jx/usb_ehci.c +++ b/src/southbridge/intel/i82801jx/usb_ehci.c @@ -11,12 +11,8 @@ static void usb_ehci_init(struct device *dev) { - u32 reg32; - printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); printk(BIOS_DEBUG, "done.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If39cdfb21fec307141593f2482e014e146d4f1f2 Gerrit-Change-Number: 40795 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40794 ) Change subject: sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND register ...................................................................... sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND register Change-Id: I5a07a00e1183ef834d97c11268935617cfe17faa Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801ix/usb_ehci.c 4 files changed, 4 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/40794/1 diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index e5b7906..434d0aa 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -247,8 +247,7 @@ pci_write_config32(dev, 0x120, reg32); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); reg8 = pci_read_config8(dev, 0x4d); // Docking Status reg8 &= ~(1 << 7); // Docking not supported diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index f26d584..b76116d 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -13,12 +13,8 @@ static void i82801ix_enable_device(struct device *dev) { - u32 reg32; - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } static void i82801ix_early_settings(const config_t *const info) diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index d170f0d..5471e69 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -20,9 +20,7 @@ printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n"); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c index 3ccffd8..9759186 100644 --- a/src/southbridge/intel/i82801ix/usb_ehci.c +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -11,12 +11,8 @@ static void usb_ehci_init(struct device *dev) { - u32 reg32; - printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); printk(BIOS_DEBUG, "done.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a07a00e1183ef834d97c11268935617cfe17faa Gerrit-Change-Number: 40794 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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