Change in coreboot[master]: soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40832 )

Change subject: soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree
......................................................................

soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree

This CL adds support to fill PcieRpClkReqDetect UPD from devicetree.
Filling this UPD will allow FSP to enable proper clksrc gpio
configuration.

BUG=None
BRANCH=None
TEST=Build and boot tglrvp.

Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7
Signed-off-by: Meera Ravindranath 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/40832/1

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index a3319d4..fe33835 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -107,6 +107,9 @@
     * clksrc. */
    uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];

+	/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
+	uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
+
    /* PCIe RP L1 substate */
    enum L1_substates_control {
    	L1_SS_FSP_DEFAULT,
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 5acad20..fc2a3c0 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -151,6 +151,11 @@
    	params->PcieRpAdvancedErrorReporting[i] =
    		config->PcieRpAdvancedErrorReporting[i];
    }
+
+	/* Enable ClkReqDetect for enabled port */
+	memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
+		sizeof(config->PcieRpClkReqDetect));
+
    /* Enable xDCI controller if enabled in devicetree and allowed */
    dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
    if (dev) {