coreboot-gerrit May 2020

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Change in coreboot[master]: soc/amd/picasso: Add UPD settings to chip.h
by Marshall Dawson (Code Review) 01 May '20

01 May '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38699 ) Change subject: soc/amd/picasso: Add UPD settings to chip.h ...................................................................... soc/amd/picasso: Add UPD settings to chip.h Add values that align with UPD settings. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I6bce44a43e57ba00d2b29cfa6249cef51e9ceabb --- M src/soc/amd/picasso/chip.h 1 file changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38699/1 diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 4e9e18b..0681277 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -44,10 +44,51 @@ I2S_PINS_I2S_TDM = 4, I2S_PINS_UNCONF = 7, /* All pads will be input mode */ } acp_pin_cfg; + + /* Options for these are in src/arch/x86/include/arch/acpi.h */ + uint8_t fadt_pm_profile; + uint16_t fadt_boot_arch; + uint32_t fadt_flags; + + /* System config index */ + uint8_t system_config; + + /* STAPM Configuration */ + uint32_t fast_ppt_limit; + uint32_t slow_ppt_limit; + uint32_t slow_ppt_time_constant; + uint32_t stapm_time_constant; + uint32_t sustained_power_limit; + + /* PROCHOT_L de-assertion Ramp Time */ + uint32_t prochot_l_deassertion_ramp_time; + + /* Lower die temperature limit */ + uint32_t thermctl_limit; + + /* FP5 Processor Voltage Supply PSI Currents. 0 indicates use SOC default */ + uint32_t psi0_current_limit; + uint32_t psi0_soc_current_limit; + uint32_t vddcr_soc_voltage_margin; + uint32_t vddcr_vdd_voltage_margin; + + /* VRM Limits. 0 indicates use SOC default */ + uint32_t vrm_maximum_current_limit; + uint32_t vrm_soc_maximum_current_limit; + uint32_t vrm_current_limit; + uint32_t vrm_soc_current_limit; + + /* Misc SMU settings */ + uint8_t sb_tsi_alert_comparator_mode_en; + uint8_t core_dldo_bypass; + uint8_t min_soc_vid_offset; + uint8_t aclk_dpm0_freq_400MHz; }; typedef struct soc_amd_picasso_config config_t; +const config_t *get_soc_config(void); + extern struct device_operations pci_domain_ops; #endif /* __PICASSO_CHIP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bce44a43e57ba00d2b29cfa6249cef51e9ceabb Gerrit-Change-Number: 38699 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: mb/google/volteer: move mipi_camera.asl to variants folders
by Nick Vaccaro (Code Review) 01 May '20

01 May '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40578 ) Change subject: mb/google/volteer: move mipi_camera.asl to variants folders ...................................................................... mb/google/volteer: move mipi_camera.asl to variants folders Moves mipi_camera.asl from mb/google/volteer/acpi/ to mb/google/volteer/variant/baseboard/include/baseboard/acpi/. Adds mipi_camera.asl to variant/[volteer|ripto]/include/acpi/. Adds VARIANT_HAS_MIPI_CAMERA, VARIANT_SPECIFIC_OPTIONS_HALVOR, VARIANT_SPECIFIC_OPTIONS_MALEFOR, VARIANT_SPECIFIC_OPTIONS_RIPTO, and VARIANT_SPECIFIC_OPTIONS_VOLTEER configs. BUG=b:154648941, b:154646959 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Ripto and Volteer to kernel. Change-Id: I2f28243dfb945857d26f27f07968a15a3eeb7a4f Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/dsdt.asl R src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl A src/mainboard/google/volteer/variants/ripto/include/variant/acpi/mipi_camera.asl A src/mainboard/google/volteer/variants/volteer/include/variant/acpi/mipi_camera.asl 5 files changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/40578/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 0870c61..b909746 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -75,4 +75,22 @@ default "ripto" if BOARD_GOOGLE_RIPTO default "volteer" if BOARD_GOOGLE_VOLTEER +config VARIANT_HAS_MIPI_CAMERA + bool + default n + +config VARIANT_SPECIFIC_OPTIONS_HALVOR + def_bool n + +config VARIANT_SPECIFIC_OPTIONS_MALEFOR + def_bool n + +config VARIANT_SPECIFIC_OPTIONS_RIPTO + def_bool n + select VARIANT_HAS_MIPI_CAMERA + +config VARIANT_SPECIFIC_OPTIONS_VOLTEER + def_bool n + select VARIANT_HAS_MIPI_CAMERA + endif # BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 640f7cd..af881ae 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -47,7 +47,10 @@ } #include <southbridge/intel/common/acpi/sleepstates.asl> + +#if CONFIG(VARIANT_HAS_MIPI_CAMERA) /* Camera */ #include <soc/intel/tigerlake/acpi/ipu.asl> - #include "acpi/mipi_camera.asl" + #include <variant/acpi/mipi_camera.asl> +#endif /* VARIANT_HAS_MIPI_CAMERA */ } diff --git a/src/mainboard/google/volteer/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl similarity index 100% rename from src/mainboard/google/volteer/acpi/mipi_camera.asl rename to src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/mipi_camera.asl new file mode 100644 index 0000000..6df5081 --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/mipi_camera.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <baseboard/acpi/mipi_camera.asl> diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/mipi_camera.asl new file mode 100644 index 0000000..6df5081 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/mipi_camera.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <baseboard/acpi/mipi_camera.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/40578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f28243dfb945857d26f27f07968a15a3eeb7a4f Gerrit-Change-Number: 40578 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: device: Constify struct device * parameter to acpi_inject_dsdt
by Furquan Shaikh (Code Review) 01 May '20

01 May '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40711 ) Change subject: device: Constify struct device * parameter to acpi_inject_dsdt ...................................................................... device: Constify struct device * parameter to acpi_inject_dsdt .acpi_inject_dsdt() does not need to modify the device structure. Hence, this change makes the struct device * parameter to acpi_inject_dsdt as const. Change-Id: I3b096d9a5a9d649193e32ea686d5de9f78124997 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/include/device/device.h M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/include/soc/acpi.h M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/vendorcode/google/chromeos/acpi.c M src/vendorcode/google/chromeos/chromeos.h 25 files changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/40711/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index efa9e8b..c21067d 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -51,7 +51,7 @@ unsigned long (*write_acpi_tables)(const struct device *dev, unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt)(const struct device *dev); - void (*acpi_inject_dsdt)(struct device *dev); + void (*acpi_inject_dsdt)(const struct device *dev); const char *(*acpi_name)(const struct device *dev); /* Returns the optional _HID (Hardware ID) */ const char *(*acpi_hid)(const struct device *dev); diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 85b40ac..8e34c85 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -267,7 +267,7 @@ gnvs->pcnt = dev_count_cpu(); } -void southbridge_inject_dsdt(struct device *device) +void southbridge_inject_dsdt(const struct device *device) { struct global_nvs_t *gnvs; diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index bf16518..68321ff 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -13,7 +13,7 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void southbridge_inject_dsdt(struct device *device); +void southbridge_inject_dsdt(const struct device *device); const char *soc_acpi_name(const struct device *dev); diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index e486c9c..cc9f634 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -272,7 +272,7 @@ gnvs->pcnt = dev_count_cpu(); } -void southbridge_inject_dsdt(struct device *device) +void southbridge_inject_dsdt(const struct device *device) { struct global_nvs_t *gnvs; diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index d6f9bed..6a74f22 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -19,7 +19,7 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void southbridge_inject_dsdt(struct device *device); +void southbridge_inject_dsdt(const struct device *device); const char *soc_acpi_name(const struct device *dev); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 1b0906f..b406096 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -483,7 +483,7 @@ } } -static void southcluster_inject_dsdt(struct device *device) +static void southcluster_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 0b68e09..1c9d6b3 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -512,7 +512,7 @@ return current; } -void southcluster_inject_dsdt(struct device *device) +void southcluster_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index 7a58bec..997b7e9 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -11,7 +11,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); -void southcluster_inject_dsdt(struct device *device); +void southcluster_inject_dsdt(const struct device *device); unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 22547fc..af3be9e 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -573,7 +573,7 @@ memset(gnvs, 0, sizeof(global_nvs_t)); } -static void southcluster_inject_dsdt(struct device *device) +static void southcluster_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 995a51d..e426fae 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -243,7 +243,7 @@ { } -void southbridge_inject_dsdt(struct device *device) +void southbridge_inject_dsdt(const struct device *device) { struct global_nvs_t *gnvs; diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index e1f9bf8..cb10f1f 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -48,7 +48,7 @@ * Creates acpi gnvs and adds it to the DSDT table. * GNVS creation is chipset specific and is done in soc specific acpi.c file. */ -void southbridge_inject_dsdt(struct device *device); +void southbridge_inject_dsdt(const struct device *device); /* * This function populates the gnvs structure in acpi table. diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d425879..6f43288 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -292,7 +292,7 @@ return current; } -void southcluster_inject_dsdt(struct device *device) +void southcluster_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 9f7e0c3..ae184e9 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -13,7 +13,7 @@ unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void southcluster_inject_dsdt(struct device *device); +void southcluster_inject_dsdt(const struct device *device); void motherboard_fill_fadt(acpi_fadt_t *fadt); #endif /* _DENVERTON_NS_ACPI_H_ */ diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index aac90c3..5ba683f 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -641,7 +641,7 @@ return acpi_align_current(current); } -void southbridge_inject_dsdt(struct device *device) +void southbridge_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index 924d9cb..f63220e 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -16,7 +16,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_mainboard_gnvs(global_nvs_t *gnvs); -void southbridge_inject_dsdt(struct device *device); +void southbridge_inject_dsdt(const struct device *device); unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); unsigned long northbridge_write_acpi_tables(const struct device *, diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 0ba0069..0fe471c 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -34,7 +34,7 @@ return current; } -void southbridge_inject_dsdt(struct device *device) +void southbridge_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 8a806be..9c5c749 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -987,7 +987,7 @@ acpigen_pop_len(); } -void southbridge_inject_dsdt(struct device *device) +void southbridge_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 215965e..35d71a4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -661,7 +661,7 @@ pch_enable(dev); } -static void southbridge_inject_dsdt(struct device *dev) +static void southbridge_inject_dsdt(const struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9b5f545..e54f2bd 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -620,7 +620,7 @@ outb(POST_OS_BOOT, 0x80); } -static void southbridge_inject_dsdt(struct device *dev) +static void southbridge_inject_dsdt(const struct device *dev) { global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index a177c6c..8765cc1 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -470,7 +470,7 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void southbridge_inject_dsdt(struct device *dev) +static void southbridge_inject_dsdt(const struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 380dca4..77a8f77 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -629,7 +629,7 @@ } } -static void southbridge_inject_dsdt(struct device *dev) +static void southbridge_inject_dsdt(const struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 242d274..4edf87e 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -559,7 +559,7 @@ pch_enable(dev); } -static void southbridge_inject_dsdt(struct device *dev) +static void southbridge_inject_dsdt(const struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d44009b..b5fb674 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -699,7 +699,7 @@ pch_enable(dev); } -static void southbridge_inject_dsdt(struct device *dev) +static void southbridge_inject_dsdt(const struct device *dev) { global_nvs_t *gnvs; diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index fad1256..abd5b67 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -35,7 +35,7 @@ acpigen_pop_len(); } -void chromeos_dsdt_generator(struct device *dev) +void chromeos_dsdt_generator(const struct device *dev) { mainboard_chromeos_acpi_generate(); } diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index f7df10f..d2d0a7a 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -70,7 +70,7 @@ */ void mainboard_chromeos_acpi_generate(void); #if CONFIG(CHROMEOS) -void chromeos_dsdt_generator(struct device *dev); +void chromeos_dsdt_generator(const struct device *dev); #else #define chromeos_dsdt_generator NULL #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/40711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b096d9a5a9d649193e32ea686d5de9f78124997 Gerrit-Change-Number: 40711 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: soc/amd/common: Add a common graphics block device driver for AMD SoCs
by Furquan Shaikh (Code Review) 01 May '20

01 May '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40675 ) Change subject: soc/amd/common: Add a common graphics block device driver for AMD SoCs ...................................................................... soc/amd/common: Add a common graphics block device driver for AMD SoCs This change adds a common graphics block device driver for AMD SoCs. In follow-up CLs, this driver will be utilized for Picasso. BUG=b:153858769 Change-Id: I45e2b98fede41e49158d9ff9f93785a34c392c22 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- A src/soc/amd/common/block/graphics/Kconfig A src/soc/amd/common/block/graphics/Makefile.inc A src/soc/amd/common/block/graphics/graphics.c 3 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/40675/1 diff --git a/src/soc/amd/common/block/graphics/Kconfig b/src/soc/amd/common/block/graphics/Kconfig new file mode 100644 index 0000000..8aa2a20 --- /dev/null +++ b/src/soc/amd/common/block/graphics/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_GRAPHICS + bool + default n + help + Select this option to use AMD common graphics driver support. diff --git a/src/soc/amd/common/block/graphics/Makefile.inc b/src/soc/amd/common/block/graphics/Makefile.inc new file mode 100644 index 0000000..3f21aaf --- /dev/null +++ b/src/soc/amd/common/block/graphics/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_GRAPHICS) += graphics.c diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c new file mode 100644 index 0000000..b21cf2c --- /dev/null +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static const struct device_operations graphics_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .ops_pci = &pci_dev_ops_pci, + .write_acpi_tables = pci_rom_write_acpi_tables, + .acpi_fill_ssdt_generator = pci_rom_ssdt, +}; + +static const unsigned short pci_device_ids[] = { + 0, +}; + +static const struct pci_driver graphics_driver __pci_driver = { + .ops = &graphics_ops, + .vendor = PCI_VENDOR_ID_ATI, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/40675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45e2b98fede41e49158d9ff9f93785a34c392c22 Gerrit-Change-Number: 40675 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 11

Change in coreboot[master]: mb/supermicro/x11: drop DeepSx config from devicetree
by Michael Niewöhner (Code Review) 01 May '20

01 May '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40858 ) Change subject: mb/supermicro/x11: drop DeepSx config from devicetree ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/40858/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40858/1//COMMIT_MSG@7 PS1, Line 7: devicetree drop DeepSx config > Yes, but the current phrasing is ungrammatical Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/40858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91cd15b26a41f376561630cf45ffa192745eae84 Gerrit-Change-Number: 40858 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 May 2020 09:02:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/*/*{i440BX}: Move serial init to bootblock
by Arthur Heymans (Code Review) 01 May '20

01 May '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39891 ) Change subject: mb/*/*{i440BX}: Move serial init to bootblock ...................................................................... mb/*/*{i440BX}: Move serial init to bootblock This moves the serial init to the bootblock. Since those boards generally don't have a large flash the console is disabled by default, but when optionally enabled the bootblock size needs to be increased. Change-Id: Icf062c93d9bd7f7a77e3d343ac8aadab038db296 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/slot_1/Kconfig A src/mainboard/asus/p2b-ds/Makefile.inc R src/mainboard/asus/p2b-ds/bootblock.c A src/mainboard/asus/p2b-ls/Makefile.inc R src/mainboard/asus/p2b-ls/bootblock.c A src/mainboard/asus/p2b/Makefile.inc R src/mainboard/asus/p2b/bootblock.c A src/mainboard/asus/p3b-f/Makefile.inc C src/mainboard/asus/p3b-f/bootblock.c M src/mainboard/asus/p3b-f/romstage.c M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i440bx/raminit.h M src/northbridge/intel/i440bx/romstage.c 13 files changed, 22 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/39891/1 diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index a8d90e8..1af9214 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -43,6 +43,7 @@ config C_ENV_BOOTBLOCK_SIZE hex + default 0x4000 if BOOTBLOCK_CONSOLE default 0x2000 endif diff --git a/src/mainboard/asus/p2b-ds/Makefile.inc b/src/mainboard/asus/p2b-ds/Makefile.inc new file mode 100644 index 0000000..8501868 --- /dev/null +++ b/src/mainboard/asus/p2b-ds/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += bootblock.c diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/bootblock.c similarity index 90% rename from src/mainboard/asus/p2b-ds/romstage.c rename to src/mainboard/asus/p2b-ds/bootblock.c index 67ba632..c30de04 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/bootblock.c @@ -13,13 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/intel/i440bx/raminit.h> +#include <bootblock_common.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -void mainboard_enable_serial(void) +void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asus/p2b-ls/Makefile.inc b/src/mainboard/asus/p2b-ls/Makefile.inc new file mode 100644 index 0000000..8501868 --- /dev/null +++ b/src/mainboard/asus/p2b-ls/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += bootblock.c diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/bootblock.c similarity index 90% rename from src/mainboard/asus/p2b-ls/romstage.c rename to src/mainboard/asus/p2b-ls/bootblock.c index 546d9ed..704dc2e 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/bootblock.c @@ -13,14 +13,14 @@ * GNU General Public License for more details. */ -#include <northbridge/intel/i440bx/raminit.h> +#include <bootblock_common.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -void mainboard_enable_serial(void) +void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asus/p2b/Makefile.inc b/src/mainboard/asus/p2b/Makefile.inc new file mode 100644 index 0000000..8501868 --- /dev/null +++ b/src/mainboard/asus/p2b/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += bootblock.c diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/bootblock.c similarity index 90% rename from src/mainboard/asus/p2b/romstage.c rename to src/mainboard/asus/p2b/bootblock.c index 67ba632..c30de04 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/bootblock.c @@ -13,13 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/intel/i440bx/raminit.h> +#include <bootblock_common.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -void mainboard_enable_serial(void) +void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asus/p3b-f/Makefile.inc b/src/mainboard/asus/p3b-f/Makefile.inc new file mode 100644 index 0000000..8501868 --- /dev/null +++ b/src/mainboard/asus/p3b-f/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += bootblock.c diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p3b-f/bootblock.c similarity index 78% copy from src/mainboard/asus/p2b-ds/romstage.c copy to src/mainboard/asus/p3b-f/bootblock.c index 67ba632..6f60077 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p3b-f/bootblock.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -13,13 +12,17 @@ * GNU General Public License for more details. */ -#include <northbridge/intel/i440bx/raminit.h> + +#include <bootblock_common.h> #include <superio/winbond/common/winbond.h> +/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> +/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -void mainboard_enable_serial(void) + +void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index e3a7897..5adb703 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -16,12 +16,6 @@ #include <arch/io.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <superio/winbond/common/winbond.h> -/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ -#include <superio/winbond/w83977tf/w83977tf.h> - -/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ -#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) /* * ASUS P3B-F specific SPD enable magic. @@ -53,8 +47,3 @@ { outb(0x67, PM_IO_BASE + 0x37); } - -void mainboard_enable_serial(void) -{ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 0161eb3..7fdf0a9 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -16,7 +16,11 @@ bool select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP - select NO_BOOTBLOCK_CONSOLE + +#these boards don't have a lot of flash so change the default +config BOOTBLOCK_CONSOLE + bool + default n config SDRAMPWR_4DIMM bool diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index dcc8007..981d473 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -22,7 +22,6 @@ void enable_spd(void); void disable_spd(void); void sdram_initialize(void); -void mainboard_enable_serial(void); /* Debug */ #if CONFIG(DEBUG_RAM_SETUP) diff --git a/src/northbridge/intel/i440bx/romstage.c b/src/northbridge/intel/i440bx/romstage.c index 1dee03a..8109c37 100644 --- a/src/northbridge/intel/i440bx/romstage.c +++ b/src/northbridge/intel/i440bx/romstage.c @@ -20,9 +20,6 @@ void mainboard_romstage_entry(void) { - mainboard_enable_serial(); - console_init(); - i82371eb_early_init(); sdram_initialize(); -- To view, visit https://review.coreboot.org/c/coreboot/+/39891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf062c93d9bd7f7a77e3d343ac8aadab038db296 Gerrit-Change-Number: 39891 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/supermicro/x11: drop DeepSx config from devicetree
by Michael Niewöhner (Code Review) 01 May '20

01 May '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40858 ) Change subject: mb/supermicro/x11: drop DeepSx config from devicetree ...................................................................... Uploaded patch set 2: Commit message was updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/40858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91cd15b26a41f376561630cf45ffa192745eae84 Gerrit-Change-Number: 40858 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 May 2020 08:55:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11: drop DeepSx config from devicetree
by Michael Niewöhner (Code Review) 01 May '20

01 May '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40858 to look at the new patch set (#2). Change subject: mb/supermicro/x11: drop DeepSx config from devicetree ...................................................................... mb/supermicro/x11: drop DeepSx config from devicetree Drop the DeepSx config as it's unsupported and disabled for the boards. Change-Id: I91cd15b26a41f376561630cf45ffa192745eae84 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/40858/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91cd15b26a41f376561630cf45ffa192745eae84 Gerrit-Change-Number: 40858 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/supermicro/x11: devicetree drop DeepSx config
by Angel Pons (Code Review) 01 May '20

01 May '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40858 ) Change subject: mb/supermicro/x11: devicetree drop DeepSx config ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/40858/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40858/1//COMMIT_MSG@7 PS1, Line 7: devicetree drop DeepSx config > well, one is the actual name of the variable the other is the name of the technology, so.... Yes, but the current phrasing is ungrammatical -- To view, visit https://review.coreboot.org/c/coreboot/+/40858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91cd15b26a41f376561630cf45ffa192745eae84 Gerrit-Change-Number: 40858 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 May 2020 08:35:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11: devicetree drop DeepSx config
by Patrick Georgi (Code Review) 01 May '20

01 May '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40858 ) Change subject: mb/supermicro/x11: devicetree drop DeepSx config ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91cd15b26a41f376561630cf45ffa192745eae84 Gerrit-Change-Number: 40858 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 01 May 2020 08:35:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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